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HT82A623R/HT82A6208/HT82A6216 A/D Type Full Speed USB 8-Bit MCU with SPI
Technical Document
* Application Note - HA0075E MCU Reset and Oscillator Circuits Application Note
Features
* Operating voltage: - VDD (MCU) * Flash Memory Block Lock protection * Single Power Supply Operation * Watchdog Timer function * 32768Hz Real time clock * Power down and wake-up functions to reduce power
fSYS = 6MHz: 2.2V~5.5V fSYS = 12MHz: 3.0V~5.5V - UBUS (USB BUS Voltage): 4.5V~5.5V - VCC (HT82A6208 & HT82A6216 for Flash): 2.8V~3.6V
* 4K15 bits Program Memory * 1608 bits Data Memory RAM * HT82A6208: 8M1 bits Flash memory structure * HT82A6216: 16M1 bits or 8Mx2 bits Flash memory
consumption
* 16 channel 12-bit resolution A/D converter * 2-channel 8-bit PWM output shared with two I/O
lines
* Up to 0.33ms instruction cycle with 12MHz system
structure
* 32 bidirectional I/O lines * USB 2.0 Full Speed Compatible * One external interrupt input shared with I/O line * Two 16-bit programmable Timer/Event Counters
clock at VDD=5V
* Max. 4 endpoints supported - endpoint 0 included * All endpoints support Interrupt, & bulk transfer * Endpoint 0 supports control, interrupt and bulk
transfer
* All endpoints except endpoint 0 can be configured
with overflow interrupt
* Two SPI interfaces (master and slave mode) shared
as 8, 16, 32, 64 FIFO size
* Endpoint 0 has 8 byte FIFO * Total FIFO size: 64+8 bytes (RAM0: 48 bytes;
with PA0~PA3, PB0~PB3
* Total of 6 Interrupts - EXT, Timer0, Timer1, SPIA,
SPIB, USB
* Flash Serial Peripheral Interface compatible - Mode0
RAM1:16 bytes, 8 bytes for endpoint0)
* 2.2V 5% LVD * 6-level subroutine nesting * Bit manipulation instruction * Table read instructions * 63 powerful instructions * All instructions executed in one or two instruction
and Mode3
* 82886081bit Flash memory structure - HT82A6208 * 167772161bit or 8388608x2bit Flash memory
structure - HT82A6216
* 256 Equal Sector with 4K byte each for Flash
memory structure- HT82A6208
* 512 Equal Sector with 4K byte each for Flash
cycles
* Low voltage reset function * Wide range of available package types
memory structure- HT82A6216
* Flash Memory Input Data Format: 1-byte Command
code
Rev. 1.10
1
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
General Description
The HT82A623R, HT82A6208 and HT82A6216 are 8-bit high performance RISC-like microcontrollers designed for USB keyboard, mouse and joystick product applications. The devices are also suitable for use in home appliances, particularly for use in high-level household appliances such as microwave ovens, washing instructions and air conditioner products. The HT82A6208 and HT82A6216 devices also possess an internal 8M or 16M Flash Memory further enhancing and expanding their application possibilities. The advantages of low power consumption, I/O flexibility, programmable frequency divider, timer functions, oscillator options, multi-channel A/D Converter, Pulse Width Modulation function, USB Interface, Watchdog timer, SPI interfaces, Power Down and wake-up functions, enhance the versatility of these devices to suit a wide range of application possibilities. The HT82A6208 contains a 8,388,608 bit serial Flash memory, which is configured as 1,048,5768 internally. The HT82A6216 contains a 16,777,216 bit serial Flash memory, which is configured as 2,097,1528 internally. The HT82A6208/HT82A6216 feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). SPI access to the device is enabled by the FHCS# input. The device provides a sequential read operation on the whole chip. After a program/erase command is issued, auto program/ erase algorithms are executed which program/erase and verify the specified page or byte/sector/block locations. A program command is executed on a page (256 bytes) basis, and an erase command is executed on a chip or sector (4K-bytes) or block (64K-bytes) basis. To provide the user with ease of interface, a status register is included to indicate the status of the device. The status read command can be issued to detect completion status of a program or erase operation via the WIP bit. When the HT82A6208/HT82A6216 is not operating and FHCS# is high, it can be put into the standby mode where it will draw less than 10mA/20mA DC current. The HT82A6208/HT82A6216 contains proprietary memory cells, which reliably store memory contents even after 100,000 program and erase cycles.
Selection Table
The following table summarises the main features of each device.
Part No. VDD VCC Program Memory Data Memory Flash Memory Timer I/O 16-bit RTC O 28SOP, 28SSOP, 48QFN 44/52QFP A/D PWM SPI Stack Package
HT82A623R
2.2V~ 5.5V 2.2V~ 5.5V
3/4
4K15
1608
3/4 8M
32
2
12-bit16 8-bit2
2
6
HT82A6208 HT82A6216
2.8V~ 3.6V
4K15
1608 16M
32
2
O
12-bit16 8-bit2
2
6
Rev. 1.10
2
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
Block Diagram
W a tc h d o g T im e r 8 - b it R IS C MCU C o re Low V o lta g e R eset W a tc h d o g T im e r O s c illa to r R eset C ir c u it In te rru p t C o n tr o lle r C ry s ta l O s c illa to r 1 C ry s ta l O s c illa to r 2 A /D C o n v e rte r S ta c k PW M G e n e ra to r
3 .3 V R e g u la to r
U S B 2 .0 XCVR
U S B 2 .0 F u ll S p e e d E n g in e
F la s h M e m o ry
SPIA In te rfa c e
SPIB In te rfa c e
O T P P ro g ra m M e m o ry
D a ta M e m o ry
I/O P o rts
8 - b it T im e r
1 6 - b it T im e r
P r o g r a m m a b le F re q u e n c y G e n e ra to r
Rev. 1.10
3
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
Pin Assignment
RES OSC4 OSC3 P D 0 /T M R 1 PD1 PD2 PD3 PD4 PD5 PD6 PD7 NC
P B 5 /A N 5 1 2 3 4 5 6 7 8 9 P B 6 /A N 6 P B 7 /A N 7 VDD UBUS D -/D A T A D + /C L K V33O OSC2 OSC1 VSS RES OSC4 OSC3
28 27 26 25 24 23 22 21 20 10 11 12 13 14 19 18 17 16 15
P B 4 /A N 4 P C 7 /A N 1 5 P C 6 /A N 1 4 P C 5 /A N 1 3 P A 7 /T M R 0 P A 6 /IN T P A 5 /P W M 1 P A 4 /P W M 0 P A 3 /S D O A P A 2 /S D IA P A 1 /S C L K A P A 0 /S C S A PD5 PD4 P A 0 /S C S A P A 1 /S C L K A P A 2 /S D IA P A 3 /S D O A P A 4 /P W M 0 P A 5 /P W M 1 P A 6 /IN T P A 7 /T M R 0 P C 0 /A N 8 P C 1 /A N 9 P C 2 /A N 1 0 P C 3 /A N 1 1 2 3 4 5 6 7 8 9 1
48 47 46 45 44 43 42 41 40 39 38 37
36 35 34 33 32
NC
H T82A 623R 4 8 Q F N -A
31 30 29 28 27
10 11
26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 /A N /A N /A N /A N /A N /A N /A N /A N /A N /A N /A N /A N
NC VSS VSS OSC1 OSC2 NC V33O D + /C L K D -/D A T A UBUS VDD
H T82A 623R 2 8 S O P -A /S S O P -A
3 /S 2 /S 1 /S 0 /S 15
4
5
6
7
12
13
14
DOB D IB CLKB CSB
P B 1 /A N 1 /S C L K B P B 2 /A N 2 /S D IB P B 3 /A N 3 /S D O B P B 4 /A N 4 P B 5 /A N 5 P B 6 /A N 6 P B 7 /A N 7 VDD UBUS D -/D A T A D + /C L K V33O FHHO LD & VCC NC FHCS# FHSO OSC2 OSC1 VSS GND & GND & FHW P FHSCLK FHSI
1 2 3 4 5 6 7 8 9 10 11 12 131415 1617 1819 20 2122 44 43 42 41403938 37 363534 33 32 31 30
P B 1 /A N 1 /S C L K B P B 2 /A N 2 /S D IB P B 3 /A N 3 /S D O B P B 4 /A N 4 P B 5 /A N 5 P B 6 /A N 6 P B 7 /A N 7 VDD UBUS D -/D A T A D + /C L K
44 43 42 41403938 37 363534 1 2 3 4 5 6 7 8 9 10 11 12 131415 1617 1819 20 2122
H T82A 6208 4 4 Q F P -A
29 28 27 26 25 24 23
PB0 PC1 PC0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
/A /A /A /T /IN /P /P /S /S /S /S
N 0 /S C S B N9 N8 MR0 T WM1 WM0 DOA D IA CLKA CSA
V33O FHHO LD & VCC NC FHCS# FHSO OSC2 OSC1 VSS GND & GND & FHW P FHSCLK FHSI
33 32 31 30
H T82A 6216 4 4 Q F P -A
29 28 27 26 25 24 23
PB0 PC1 PC0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
/A /A /A /T /IN /P /P /S /S /S /S
N 0 /S C S B N9 N8 MR0 T WM1 WM0 DOA D IA CLKA CSA
D -/D A T A D + /C L K V33O NC FHCS# FHSO VC C & FH HO LD OSC2 OSC1 VSS & VSS & VSS GND & GND & FHW P FHSCLK FHSI
1 2 3 4 5 6 7 8 10 11 12 13 9
52515049484746454443424140
14151617181920212223242526 NC
PD7 PD6 PD5 PD4 PD3 PD2 PD1 P D 0 /T M R 1 OSC3 OSC4 RES P C 5 /A N 1 3 P C 6 /A N 1 4 P C 7 /A N 1 5 P B 0 /A N 0 /S C S B P B 1 /A N 1 /S C L K B P B 2 /A N 2 /S D IB P B 3 /A N 3 /S D O B P B 4 /A N 4 P B 5 /A N 5 P B 6 /A N 6 P B 7 /A N 7 VDD UBUS 39 38 37 36 H T82A 6208 H T82A 6216 5 2 Q F P -A 35 34 33 32 31 30 29 28 27 PC4 PC3 PC2 PC1 PC0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 /A N /A N /A N /A N /A N /T M /IN T /P W /P W /D S /S D /S C /S C 12 11 10 8 R0 M0 OA IA LKA SA M1 9 NC PD7 PD6 PD5 PD4 PD3 PD2 PD1 P D 0 /T M R 1 OSC3 OSC4 RES
PD7 PD6 PD5 PD4 PD3 PD2 PD1 P D 0 /T M R 1 OSC3 OSC4 RES
Rev. 1.10
4
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
Pin Description
Pin Name PA0/SCSA PA1/SCLKA PA2/SDIA PA3/SDOA PA4/PWM0 PA5/PWM1 PA6/INT PA7/TMR0 PB0/AN0/SCSB PB1/AN1/SCLKB PB2/AN2/SDIB PB3/AN3/SDOB PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7/VDDIO I/O Options Description Bidirectional 8-bit input/output port. Each pin can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors. The INTB and TMR0 pins are pin-shared with PA6 and PA7 respectively. PA0~PA3 are shared with the SPIA function. PA4~PA5 are shared with PWM0 and PWM1.
I/O
Pull-high Wake-up NMOS or CMOS
I/O
Bidirectional 8-bit input/output port. Each nibble, PB0~PB3 and PB4~PB7 pin can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger Pull-high input. Configuration options determine if the pins have pull-high resistors. Wake-up PB is pin shared with the A/D inputs. Once a PB line is selected as an A/D PB7/VDDIO input using software control, the I/O function and pull-high resistor are disPB0~PB6 abled automatically. PB7 can be configured as a normal I/O or a VDDIO pin with VDDIO by configuration option. The power supply for pins PB0~PB6 can be set to either VDD or VDDIO by configuration options. PB0~PB3 are shared with SPIB. Bidirectional 8-bit input/output port. Each nibble, PC0~PC3 and PC4~PC7 pin can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors. PC is pin shared with the A/D inputs. Once a PC line is selected as an A/D input using software control, the I/O function and pull-high resistor are disabled automatically. Bi-directional 8-bit input/output port. Each nibble, PD0~PD3 and PD4~PD7 pin can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors. The TMR1 pin is shared with PD0. USBD- line USBD+ line 3.3V regulator output USB SIE VDD OSC1, OSC2 are connected to an external 6MHz or 12MHz Crystal/resonator, determined by software instructions, for the internal system clock Real time clock oscillator. OSC3, OSC4 are connected to a 32768Hz crystal oscillator for timing purposes or to a system clock source (depending on the options). No built-in capacitor. Schmitt trigger reset input. Active low Positive power supply of MCU except for USBSIE Flash Memory chip select Flash Memory Serial data input Flash Memory Serial data output Flash Memory Clock input Flash Memory HOLD, to pause the device without deselecting the device Flash Memory Write protection HT82A6208 and HT82A6216 Flash Memory Positive Power Supply
PC0/AN8~ PC7/AN15
I/O
Pull-high Wake-up
PD0/TMR1 PD1~PD7
I/O
Pull-high Wake-up
D-/DATA D+/CLK V33O UBUS OSC1 OSC2 OSC3 OSC4 RES VDD FHCS# FHSI FHSO FHSCLK FHHOLD FHWP VCC Note:
I/O I/O O 3/4 I O I O I 3/4 I I O I I I 3/4
3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
The Pin Description reflects the situation of the largest package, smaller package types may not contain all pins described in the table. 5 October 30, 2009
Rev. 1.10
HT82A623R/HT82A6208/HT82A6216
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................150mA Total Power Dissipation .....................................500mW Storage Temperature ............................-50C to 125C Operating Temperature...............................0C to 70C IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol Parameter Test Conditions VDD 3/4 3/4 3/4 5V 5V Conditions fSYS=6MHz fSYS=12MHz 3/4 3/4 No load, fSYS=12MHz, ADC Off, DAC Off No load, fSYS=12MHz, ADC On, DAC On No load, system HALT, USB transceiver and 3.3V regulator on No load ,system HALT, PS MODE, Set SUSP2 [UCC.4] 3/4 3/4 3/4 3/4 3/4 IV33O=-5mA 3/4 3/4 3/4 VOL=0.1VDD VOH=0.9VDD 3/4 3/4 3/4 No load 3/4 3/4 3/4 Min. 2.2 3.0 2.8 4.5 3/4 3/4 3/4 Typ. 3/4 3/4 3.3 3/4 8 12 Max. 5.5 5.5 3.6 5.5 3/4 3/4
Ta=25C Unit V V V V mA mA
VDD VCC UBUS IDD1 IDD2
MCU Operating Voltage HT82A6208 and HT82A6216 Flash Memory Operating Voltage USB SIE Operating Voltage Operating Current Operating Current
ISUS
Suspend Current
5V
330
500
mA
ISTB VIL1 VIH1 VIL2 VIH2 VLVR0 VV33O VAD VOS VLVD IOL IOH RPH RPH1 RPH2 IADC DNL INL RESOLU
Standby Current (WDT Disabled) Input Low Voltage for I/O Ports Input High Voltage for I/O Ports Input Low Voltage (RES) Input High Voltage (RES) Low Voltage Reset 3.3V Regulator Output 12-bit A/D Input Voltage Offset Error Low Voltage Detect I/O Port Sink Current I/O Port Source Current Pull-high Resistance Pull-high Resistance for DATA Pull-high Resistance for CLK Additional Power Consumption if A/D Converter is Used A/D Differential Non-Linearity A/D Integral Non-Linearity Resolution
5V 5V 5V 5V 5V 5V 5V 3/4 3/4 3/4 5V 5V 5V 5V 5V 5V 3/4 3/4 3/4
3/4 0 0.7VDD 0 0.8VDD 1.9 3.0 0 -2 2.1 10 -5 10 3/4 3/4 3/4 3/4
3/4 3/4 3/4 3/4 3/4 2.0 3.3 3/4 3/4 2.2 20 -10 30 4.5 4.5 1.5 3/4 2.5
10 0.3VDD VDD 0.4VDD VDD 2.1 3.6 VDD 2 2.3 3/4 3/4 50 3/4 3/4 3.0 2 4.0 12
mA V V V V V V V mV MHz mA mA kW kW kW mA LSB LSB Bits
Rev. 1.10
6
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
A.C. Characteristics
Test Conditions Symbol Parameter VDD fSYS System Clock Timer I/P Frequency (TMR0/TMR1) Watchdog Oscillator Period External Reset Low Pulse Width System Start-up Timer Period Option Load Timer Period Interrupt Pulse Width A/D Clock Period A/D Conversion Time A/D Sample Time SPI SCSA or SCSB to SCLKA or SCLKB Time SPI Clock Time 3/4 3/4 3/4 5V 3/4 3/4 5V 3/4 3/4 3/4 3/4 3/4 3/4 Conditions 2.2V~5.5V 3.0V~5.5V fSYS=6MHz fSYS=12MHz 3/4 3/4 Wake-up from HALT 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0 3/4 1 3/4 33 1 1 3/4 3/4 50 166 6000 12000 3/4 3/4 65 3/4 1024 70 3/4 3/4 16 8 3/4 3/4 3/4 3/4 6000 12000 3/4 3/4 3/4 140 3/4 3/4 3/4 3/4 3/4 3/4 kHz kHz kHz kHz ms ms tSYS ms ms ms tAD tAD ns ns Min. Typ. Max. Unit Ta=25C
fTIMER tWDTOSC tRES tSST tOPD tINT tAD tADC tADCS tCS_SK tSPICK
Note: tSYS=1/fSYS
Rev. 1.10
7
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to the internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O and A/D control system with maximum reliability and flexibility. Clocking and Pipelining The main system clock, derived from a Crystal/Resonator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. For instructions involving branches, such as jump or call instructions, two instruction cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.
O s c illa to r C lo c k ( S y s te m C lo c k ) P h a s e C lo c k T 1 P h a s e C lo c k T 2 P h a s e C lo c k T 3 P h a s e C lo c k T 4 P ro g ra m C o u n te r PC PC+1 PC+2
P ip e lin in g
F e tc h In s t. (P C ) E x e c u te In s t. (P C -1 )
F e tc h In s t. (P C + 1 ) E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 ) E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
1 2 3 4 5 6 D ELAY: : :
M O V A ,[1 2 H ] C ALL D ELAY C P L [1 2 H ]
F e tc h In s t. 1
E x e c u te In s t. 1 F e tc h In s t. 2 E x e c u te In s t. 2 F e tc h In s t. 3 F lu s h P ip e lin e F e tc h In s t. 6 E x e c u te In s t. 6 F e tc h In s t. 7
NOP
Instruction Fetching
Rev. 1.10
8
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as JMP or CALL that demand a jump to a non-consecutive Program Memory address. It must be noted that only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by user. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. The lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL might cause program branching, so an extra cycle is needed to pre-fetch. Further information on the PCL register can be found in the Special Function Register section. Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack has 6 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, SP, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack.
P ro g ra m C o u n te r
T o p o f S ta c k S ta c k P o in te r
S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k L e v e l 3 P ro g ra m M e m o ry
B o tto m
o f S ta c k
S ta c k L e v e l 6
Program Counter Bits Mode b11 Initial Reset USB Interrupt External Interrupt Timer/Event Counter 0 Overflow SPIA Interrupt SPIB Interrupt Timer/Event Counter 1 Overflow Skip Loading PCL Jump, Call Branch Return from Subroutine PC11 PC10 #11 S11 #10 S10 PC9 #9 S9 PC8 #8 S8 0 0 0 0 0 0 0 b10 0 0 0 0 0 0 0 b9 0 0 0 0 0 0 0 b8 0 0 0 0 0 0 0 b7 0 0 0 0 0 0 0 b6 0 0 0 0 0 0 0 b5 0 0 0 0 0 0 0 b4 0 0 0 0 1 1 1 b3 0 0 1 1 0 0 1 b2 0 1 0 1 0 1 0 b1 0 0 0 0 0 0 0 b0 0 0 0 0 0 0 0
Program Counter + 2 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0
Program Counter Note: PC11~PC8: Current Program Counter bits #11~#0: Instruction code address bits @7~@0: PCL bits S11~S0: Stack register bits
Rev. 1.10
9
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. Arithmetic and Logic Unit - ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions:
* Arithmetic operations: ADD, ADDM, ADC, ADCM,
000H 004H 008H 00CH 010H 014H 018H
In itia lis a tio n V e c to r USB In te rru p t V e c to r E x te rn a l In te rru p t V e c to r T im e r /E v e n t C o u n te r 0 In te rru p t V e c to r S P IA In te rru p t V e c to r S P IB In te rru p t V e c to r T im e r /E v e n t C o u n te r 1 In te rru p t V e c to r
FFFH
1 5 b its
Program Memory Structure Special Vectors Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts.
* Location 000H
SUB, SUBM, SBC, SBCM, DAA
* Logic operations: AND, OR, XOR, ANDM, ORM,
This vector is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution.
* Location 004H
XORM, CPL, CPLA
* Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
RLC
* Increment and Decrement INCA, INC, DECA, DEC * Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,
This area is reserved for the USB interrupt service program. If the USB interrupt is activated, the interrupt is enabled and the stack is not full, the program will jump to this location and begin execution.
* Location 008H
SIZA, SDZA, CALL, RET, RETI
Program Memory
The Program Memory is the location where the user code or program is stored. The HT82A623R is a One-Time Programmable, OTP, memory type device where users can program their application code into the device. By using the appropriate programming tools, OTP devices offer users the flexibility to freely develop their applications which may be useful during debug or for products requiring frequent upgrades or program changes. OTP devices are also applicable for use in applications that require low or medium volume production runs. Structure The Program Memory has a capacity of 4K by 15 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by separate table pointer registers.
This vector is used by the external interrupt. If the INT external input pin on the device receives a high to low transition, the program will jump to this location and begin execution, if the interrupt is enabled and the stack is not full.
* Location 00CH
This vector is used by the timer0 counter. If a counter overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full.
* Location 010H
This vector is used by serial interface A . When 8-bits of data have been received or transmitted successfully from serial interface A, the program will jump to this location and begin execution if the interrupt is enabled and the stack is not full.
* Location 014H
This vector is used by serial interface B . When 8-bits of data have been received or transmitted successfully from serial interface A, the program will jump to this location and begin execution if the interrupt is enabled and the stack is not full
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* Location 018H
TBHP TBLP
This vector is used by the timer1 counter. If a counter overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full. Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, one method is to first setup a low byte table pointer by placing the lower order address of the look up data to be retrieved in the low byte table pointer register, TBLP. This register defines the lower 8-bit address of the look-up table. After setting up the table pointer, the table data can be retrieved from the current Program Memory page or last Program Memory page using the TABRDC[m] or TABRDL [m] instructions, respectively. When these instructions are executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as 0. The following diagram illustrates the addressing/data flow of the look-up table:
P ro g ra m C o u n te r H ig h B y te TBLP P ro g ra m M e m o ry
P ro g ra m M e m o ry
TBLH H ig h B y te o f T a b le C o n te n ts
S p e c ifie d b y [m ] Low B y te o f T a b le C o n te n ts
Table Read - TBLP/TBHP Table Program Example Another method is to setup the full table address using both the TBLP and TBHP low and high byte table pointer registers to directly address any area in he Program Memory. In this way any page of data can be accessed directly using the TABRDL instruction. If the TBHP high byte table pointer register is to be used, then it must first be enabled with a configuration option. The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the last page which is stored there using the ORG statement. The value at this ORG statement is F00H which refers to the start address of the last page within the 4K Program Memory of device. The table pointer is setup here to have an initial value of 06H. This will ensure that the first data read from the data table will be at the Program Memory address F06H or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the TABRDC [m] instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the TABRDL [m] instruction is executed.
TBLH T a b le C o n te n ts H ig h B y te
S p e c ifie d b y [m ] T a b le C o n te n ts L o w B y te
Table Read - TBLP only
Instruction TABRDC [m] TABRDL [m]
Table Location Bits b11 PC11 1 b10 PC10 1 b9 PC9 1 b8 PC8 1 b7 @7 @7 b6 @6 @6 b5 @5 @5 b4 @4 @4 b3 @3 @3 b2 @2 @2 b1 @1 @1 b0 @0 @0
Table Location Note: PC11~PC8: Current Program Counter bits @7~@0: Table Pointer TBLP bits TBHP register bit3~bit0 when TBHP is enabled
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* Table Program Example
tempreg1 db tempreg2 db : : mov a,06h mov tblp,a : : tabrdl
? ?
; temporary register #1 ; temporary register #2
; initialise table pointer - note that this address ; is referenced ; to the last page or present page
tempreg1
; ; ; ;
transfers value in table referenced by table pointer to tempregl data at prog. memory address F06H transferred to tempreg1 and TBLH
dec tblp tabrdl tempreg2
; reduce value of table pointer by one ; ; ; ; ; ; ; ; transfers value in table referenced by table pointer to tempreg2 data at prog.memory address F05H transferred to tempreg2 and TBLH in this example the data 1AH is transferred to tempreg1 and data 0FH to register tempreg2 the value 00H will be transferred to the high byte register TBLH
: : org F00h dc ; sets initial address of last page
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : :
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Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use the table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. microcontrollers, such as ACC, PCL, etc., have the same Data Memory address. General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user program for both read and write operations. By using the SET [m].i and CLR [m].i instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory.
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0C H 0D H 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1C H 1D H 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2C H 2D H IA M IA M R0 P0 R1 P1 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H PW PW PW PW PW MB M0 MB M1 NC R0 DR R1 DR TL A SBC SBD AD AD AD AC SBC SBD MO S P I_ RA RL RH CR SR RB RB DE REG RA H UFOEN UFC0
Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into two sections, the first of these is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. Structure The two sections of Data Memory, the Special Purpose and General Purpose Data Memory are located at consecutive locations. All are implemented in RAM and are 8 bits wide but the length of each memory section is dictated by the type of microcontroller chosen. The start address of the Data Memory for all devices is the address 00H. Registers which are common to all
00H Spec P u rp o Da M em o ia l se ta ry 5FH 60H G e n e ra l P u rp o s e D a ta M e m o ry FFH
ACC PCL TBLP TBLH W DTS STATUS IN T C 0 TM R1H TM R1L TM R1C TM R0H TM R0L TM R0C PA PAC PB PBC PC PCC PD PDC U SB_STAT U IN T IN T C 1 TBHP USC USR UCC AW R STALL S IE S M IS C U F IE N F IF O 0 F IF O 1 F IF O 2 F IF O 3
Data Memory Structure Note: Most of the Data Memory bits can be directly manipulated using the SET [m].i and CLR [m].i with the exception of a few dedicated bits. The Data Memory can also be accessed through the memory pointer register MP. 13
: U n u s e d R e a d a s "0 0 "
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Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writable but some are protected and are readable only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value 00H. physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointer, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together only access data from Bank 0, while the IAR1 and MP1 register pair can access data from both Bank 0 and Bank 1. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of 00H and writing to the registers indirectly will result in no operation. Memory Pointer - MP0, MP1 For all devices, two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related Memory Pointer.
Special Function Registers
To ensure successful operation of the microcontroller, certain internal registers are implemented in the Data Memory area. These registers ensure correct operation of internal functions such as timers, interrupts, etc., as well as external functions such as I/O data control. The location of these registers within the Data Memory begins at the address 00H. Any unused Data Memory locations between these special function registers and the point where the General Purpose Memory begins is reserved and attempting to read data from these locations will return a value of 00H. Indirect Addressing Register - IAR0, IAR1 The IAR0 and IAR1 register, although having their locations in normal RAM register space, do not actually
data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov mov mov mov loop: clr inc sdz jmp a,04h ; setup size of block block,a a,offset adres1; Accumulator loaded with first RAM address mp0,a ; setup memory pointer with first RAM address IAR0 mp0 block loop ; clear the data at address defined by MP0 ; increment memory pointer ; check if last memory location has been cleared
continue: The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses.
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Accumulator - ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register - PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers - TBLP, TBHP, TBLH These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointer low and high byte registers and indicate the location where the table data is located. There value must be setup before any table read commands are executed. Their value can be changed, for example using the INC or DEC instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location.
b7 TO PDF OV Z AC
Status Register - STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the CLR WDT or HALT instruction. The PDF flag is affected only by executing the HALT or CLR WDT instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations.
* C is set if an operation results in a carry during an ad-
dition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.
* AC is set if an operation results in a carry out of the
low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.
* Z is set if the result of an arithmetic or logical operation
is zero; otherwise Z is cleared.
* OV is set if an operation results in a carry into the high-
est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
* PDF is cleared by a system power-up or executing the
CLR WDT instruction. PDF is set by executing the HALT instruction.
* TO is cleared by a system power-up or executing the
CLR WDT or HALT instruction. TO is set by a WDT time-out.
b0 C
S T A T U S R e g is te r
Ar Ca Au Ze ith m e r r y fla x ilia r y r o fla g O v e r flo w g tic /L o g ic O p e r a tio n F la g s c a r r y fla g fla g an n tim e a g e m e n t F la g s fla g e - o u t fla g n te d , re a d a s "0 "
S y s te m M Pow erdow W a tc h d o g N o t im p le m
Status Register
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In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the interrupt routine can change the status register, precautions must be taken to correctly save it. Interrupt Control Registers - INTC0, INTC1 The microcontrollers provide one external interrupt, two internal timer/event counter overflow interrupts, two SPI interrupts and one USB interrupt. By setting various bits within these registers using standard bit manipulation instructions, the enable/disable function of each interrupt can be independently controlled. A master interrupt bit within this register, the EMI bit, acts like a global enable/disable and is used to set all of the interrupt enable bits on or off. This bit is cleared when an interrupt routine is entered to disable further interrupt and is set by executing the RETI instruction. Timer/Event Counter Registers TMR0H/TMR1H, TMR0L/TMR1L,TMR0C/TMR1C All devices possess two internal 16-bit count-up timer. An associated register pair known as TMR0L/TMR0H and TMR1L/TMR1H are the locations where the timer 16-bit values are located. These registers can also be preloaded with fixed data to allow different time intervals to be setup. Associated control registers, known as TMR0C and TMR1C, contains the setup information for the timers, which determines in what mode the timer is to be used as well as containing the timer on/off control function. Input/Output Ports and Control Registers Within the area of Special Function Registers, the I/O registers and their associated control registers play a prominent role. All I/O ports have a designated register correspondingly labeled as PA, PB, PC and PD. These labeled I/O registers are mapped to specific addresses within the Data Memory as shown in the Data Memory table, which are used to transfer the appropriate output or input data on that port. With each I/O port there is an associated control register labeled PAC, PBC, PCC and PDC, also mapped to specific addresses with the Data Memory. The control register specifies which pins of that port are set as inputs and which are set as outputs. To setup a pin as an input, the corresponding bit of the control register must be set high, for an output it must be set low. During program initialisation, it is important to first setup the control registers to specify which pins are outputs and which are inputs before reading data from or writing data to the I/O ports. One flexible feature of these registers is the ability to directly program single bits using the SET [m].i and CLR [m].i instructions. The ability to change I/O pins from output to input and vice versa by manipulating specific bits of the I/O control registers during normal program operation is a useful feature of these devices.
Flash Memory
The HT82A6208 contains a 8,388,608 bit serial Flash memory, which has an internal configuration of 1,048,5768. The HT82A6208 internal Flash Memory contains a 16,777,216 bit serial Flash memory, with a 2,097,1528 internal configuration. The HT82A623R does not contain Flash Memory. Device HT82A623R HT82A6208 HT82A6216 Size 3/4 8M 16M Configuration 3/4 1,048,5768 2,097,1528
Flash Memory Description The HT82A6208/HT82A6216 internal Flash Memory feature a serial peripheral interface and software protocol which permits operation using a simple 3-wire bus. The three bus signals are a clock input, FHSCLK, serial data input, FHSI, and serial data output, FHSO. The SPI access to the device is enabled using the FHCS# input. There is a sequential read operation for the whole device. After a program/erase command is issued, the auto program/erase algorithms which program/erase and verify the specified page or byte/sector/block locations will be executed. Program command is executed on a page, 256 byte, basis, and an erase command is executed on chip or sector, 4K-bytes, or block, 64K-bytes. To provide the user with a simplistic interface, a status register is included to indicate the status of the device. The status read command can be issued to detect a completion status of a program or erase operation using the WIP bit. When the HT82A6208/HT82A6216 internal Flash Memory is not in operation and FHCS# is high, the device will be place into a standby mode where it will draw less than 10mA/20mA DC current. The HT82A6208/HT82A6216 internal Flash Memory reliably stores its memory contents even after 100,000 program and erase cycles. Data Protection The device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state instruction in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorpo-
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rates several features to prevent inadvertent write cycles during power-on and power-down transitions or due to system noise. These features are:
* Power-on reset and tPUW: to avoid problems due to sys-
Status Bit BP2 1 1 1 1 BP1 0 0 1 1 BP0 0 1 0 1
Protect Level 4 (8 blocks) 5 (all) 6 (all) 7 (all)
8Mb Block 8~15 All All All
tem power supply transitions, the power-on reset and tPUW (internal timer) may protect the Flash Memory.
* Valid command length checking: The command
length will be checked whether it is at byte base and completed on byte boundary.
* Write Enable (WREN) command: The WREN com-
Protected Flash Area - HT82A6208 Status Bit BP3 BP2 BP1 BP0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 (none) 1 (1block, block 31th) 2 (2blocks, block 30~31th) 3 (4blocks, block 28~31th) 4 (8blocks, block 24~31th) 5 (16blocks, block 16~31th) 6 (32blocks, all) 7 (32blocks, all) 8 (32blocks, all) 9 (32blocks, all) 10 (16blocks, block 0~15th) 11 (24blocks, block 0~23th) 12 (28blocks, block 0~27th) 13 (30blocks, block 0~29th) 14 (31blocks, block 0~30th) 15 (32blocks, all)
mand is required to set the Write Enable Latch bit (WEL) before other commands to change data. The WEL bit will return to its reset condition under the following situations: Power-on

16Mb
Write Disable (WRDI) command completion Write Status Register (WRSR) command completion Page Program (PP) command completion Continuous Program mode (CP) instruction completion - only for HT82A6216 internal Flash Memory Sector Erase (SE) command completion Block Erase (BE) command completion Chip Erase (CE) command completion Write Read-lock Bit (WRLB) instruction completion - only for HT82A6216 internal Flash Memory

* Deep Power Down Mode: By entering the deep power
down mode, the flash memory is also under protection from all write commands except for the Release from deep power down mode command (RDP) and Read Electronic Signature command (RES).
* Software Protection Mode (SPM): by using the BP
Protected Flash Area - HT82A6216 Hold Features The FHHOLD pin signal goes low to hold any serial communications with the device. The HOLD features will not stop the function of the write status register or any programming erase operation in progress. The HOLD operation requires that the Chip Select, (FHCS#) is kept low and starts on the falling edge of the FHHOLD pin signal while the Serial Clock (FHSCLK) signal is low (if Serial Clock signal is not being low. The HOLD operation will not start until the Serial Clock is low). The HOLD condition ends on the rising edge of the FHHOLD pin signal white the Serial Clock (FHSCLK)
register bits BP0~BP3, sections of the Flash Memory can be protected.
* Hardware Protection Mode (HPM): keeping WP low
will protect the BP0~BP3 bits and the SRWD bit from a state change. Status Bit BP2 0 0 0 0 BP1 0 0 1 1 BP0 0 1 0 1 Protect Level 0 (none) 1 (1 block) 2 (2 blocks) 3 (4 blocks) 8Mb None Block 15 Block 14~15 Block 12~15
FHCS# FHSCLK FHHOLD
Figure 1. Hold Condition Operation
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signal is low. If the Serial Clock signal is low, the HOLD operation will not end until the Serial Clock being is low for the following figure 1. The Serial Data Output (FHSO) is high impedance, both Serial Data Input (FHSI) and Serial Clock (FHSCLK) are dont care during the HOLD operation. If the Chip Select (FHCS#) is set high during the HOLD operation then it will reset the internal logic of the device. To re-start communication with the device, the FHHOLD pin must be high and FHCS# must be low. For the HT82A6208/HT82A6216, the internal Flash Memory FHHOLD pin must is bound to the VCC pin. Memory Organisation The internal memory blocks of the Flash Memory including the sector and address range is shown in the following tables.
Table 1. Flash Memory Organisation - HT82A6208
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Table 2. 16Mb Flash Memory Organisation HT82A6216
Table 2. 16Mb Flah Memory Organisation HT82A6216
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Command Definitions The internal Flash Memory operates using a range of commands issued serially by the microcontroller to the Flash Memory. These commands are summarised in the accompanying table.
FHCS# goes high
Flash Memory Command Definition - HT82A6208
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FHCS#
FHCS# FHCS#
Flash Memory Command Definition - HT82A6216
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Flash Memory Operation The following statements show the basic protocol behind each Flash Memory command execution.
* Before a command is issued, the status register
The sequence to execute the WREN instruction is: FHCS# goes low (R) send WREN instruction code (R) FHCS# goes high.
FHCS#
should be checked to ensure that the device is ready for the intended operation.
* When a correct command is input to the device, it will
FHSCLK
enter the standby mode and remain in the standby mode until the next FHCS# falling edge. In the standby mode, the device FHSO pin should be High-Z.
* When a correct command is input to the device, it will
FHSI
FHSO
enter the active mode and remain in the active mode until the next FHCS# rising edge.
* The input data is latched on the rising edge of the Se-
Write Enable (WREN) Sequence (Command 06)
* Write Disable - WRDI
rial Clock, FHSCLK, and the data is shifted out on the falling edge of FHSCLK. The difference between SPI mode 0 and mode 3 is shown in Figure 2.
* For the following instructions: RDID, RDSR, READ,
The Write Disable, WRDI, instruction is for resetting the Write Enable Latch, WEL, bit. The sequence of issuing the WRDI instruction is: FHCS# goes low (R) send WRDI instruction code (R) FHCS# goes high.
FHCS#
FAST_READ, RES and REMS the shifted-in instruction sequence is followed by a data-out sequence. After any data bit is shifted out, FSCS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP and DP, CS must go high exactly at the byte boundary; otherwise the instruction will be rejected and not executed.
* During the progress of Write Status Register, Pro-
FHSCLK
FHSI
gram, Erase operations, the memory array access is neglected and therefore does not affect the current operation of the Write Status Register, Program, Erase. Command Description The following provides a detailed description of each Flash Memory Command.
* Write Enable - WREN
FHSO
Write Disable (WRDI) Sequence (Command 04) The WEL bit is reset by following conditions:

Power-up Write Disable, WRDI, instruction completion Write Status Register (WRSR) instruction completion Page Program (PP) instruction completion Sector Erase (SE) instruction completion Block Erase (BE) instruction completion Chip Erase (CE) instruction completion
The Write Enable, WREN, instruction is used to set the Write Enable Latch, WEL, bit. For instructions like PP, SE, BE, CE, and WRSR, which are intended to change the device contents, it should be set every time after the WREN instruction sets the WEL bit.
FHSCLK
FHSCLK
FHSI
FHSO
Note:
CPOL indicates clock polarity of the SPI master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of the CPOL bit and CPHA bit decides which SPI mode is supported. Figure 2. Supported SPI Modes 22 October 30, 2009
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* Read Identification - RDID
The RDID instruction is for reading the manufacturer 1-byte ID followed by the 2-byte Device ID. The device Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte device ID, and the individual device ID of second-byte ID is as follows: 14(hex) for the HT82A6208/HT82A6216 internal Flash Memory. The sequence for issuing the RDID instruction is: FHCS# goes low (R) sending RDID instruction code (R) 24-bits ID data out on SO (R) to end RDID operation can use FHCS# high at any time during data out. While the Program/Erase operation is in progress, it will not decode the RDID instruction, so there is no effect on the cycle of program/erase operation which is currently in progress. When FHCS# goes high, the device is in the standby stage.
* Read Status Register - RDSR
The definition of the status register bits is shown below:
The instruction is for reading the Status Register Bits. The Read Status Register can be read at any time (even in the program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence to issue the RDSR instruction is: FHCS# goes low (R) sending RDSR instruction code (R) Status Register data out on SO.
WIP bit The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When the WIP bit is set to 1, this means the device is busy in program/erase/write status register progress. When the WIP bit is set to 0, this means the device is not in progress of program/erase/write status register cycle. WEL bit The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When the WEL bit is set to 1, which means the internal write enable latch is set, the device can accept program/erase/write status register instructions. When the WEL bit is cleared to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instructions. BP0~BP3 Bits The Block Protect bits BP0~BP3, are non-volatile bits, which indicate the protected area (as defined in the table) of the device against the program/erase instruction without the hardware protection mode being set. To write the Block Protect bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of
FHCS#
FHSCLK
FHSI
FHSO
Read Identification (RDID) Sequence (Command 9F)
FHCS#
FHSCLK
FHSI
FHSO
Read Status Register (RDSR) Sequence (Command 05)
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the memory against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase(CE) instructions (only if all Block Protect bits are set to 0, can the CE instruction be executed).
* Write Status Register - WRSR
SRWD bit The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with the Write Protection (FHWP) pin to provide the hardware protection mode. The hardware protection mode requires that SRWD is set to 1 and the WP# pin signal is low . In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP0~BP3) are read only. For the HT82A6208/HT82A6216 internal Flash memory, the Write Protection (FHWP) pin is always bonded with the GND pin
The WRSR instruction is used to change the values of the Status Register Bits. Before sending an WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of the Block Protect (BP0~BP3) bits to define the protected area of memory (as shown in the table). The WRSR also can set or reset the Status Register Write Disable (SRWD) bit in accordance with the Write Protection (WP#) pin signal. The WRSR instruction cannot be executed once the Hardware Protected Mode is entered. The sequence to issue WRSR instruction is: FHCS# goes low (R) sending WRSR instruction code (R) Status Register data on SI (R) FHCS# goes high. (see Figure 3). The WRSR instruction has no effect on b6, b5, b1, b0 of the status register.
FHCS#
FHSCLK
FHSI
FHSO
Figure 3. Write Status Register (WRSR) Sequence (Command 01)
Note:
1. See the table Protected Flash Area . 2. The endurance cycles for the protect bits are 100,000 cycles; however, the tW time out spec for the protect bits is relaxed to tW = N 15ms (N is a multiple of 10,000 cycles, ex. N = 2 for 20,000 cycles) after 10,000 cycles on those bits. Status Register - HT82A6208 Internal Flash Memory
Note:
See the table Protected Flash Area Status Register - HT82A6216 Internal Flash Memory
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FHWP FHWP FHWP FHWP
FHWP
Note:
As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 1. The above table shows the summary of the Software Protected Mode, SPM, and Hardware Protected Mode, HPM. Software Protected Mode - SPM:
* When the SRWD bit=0, no matter if FHWP is low or high, the WREN instruction may set the WEL bit and can
change the values of SRWD, BP2, BP1, BP0. The protected area, which is defined by bits BP2, BP1, BP0, is in the software protected mode.
* When the SRWD bit=1 and FHWP is high, the WREN instruction may set the WEL bit and can change the
values of SRWD, BP2, BP1, BP0. The protected area, which is defined by BP2, BP1, BP0, is in the software protected mode. Note: If SRWD bit=1 but FHWP is low, it is impossible to write to the Status Register even if the WEL bit has previously been set. Hardware Protected Mode - HPM:
* When the SRWD bit=1, and then FHWP is low (or FHWP is low before SRWD bit=1), the device enters the
hardware protected mode. The protected area data, defined by bits BP2, BP1, BP0 and hardware protected mode using FHWP is protected against data modification. Note: to exit the hardware protected mode requires that FHWP is set high once the hardware protected mode is entered. If the FHWP pin is permanently connected high, the hardware protected mode can never be entered; only software can be used to enter the protected mode via bits BP2, BP1, BP0. Protection Modes - HT82A6208 Internal Flash Memory
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FHWP FHWP FHWP FHWP
FHWP
Note:
As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 1. The above table shows the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM). Software Protected Mode - SPM:
* When the SRWD bit=0, no matter if FHWP/ACC is low or high, the WREN instruction may set the WEL bit
and can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is in the software protected mode (SPM).
* When the SRWD bit=1 and FHWP/ACC is high, the WREN instruction may set the WEL bit and can change
the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is in the software protected mode (SPM) Note: If the SRWD bit=1 but FHWP/ACC is low, it is impossible to write to the Status Register even if the WEL bit has previously been set. It is rejected to write to the Status Register and not be executed. Hardware Protected Mode - HPM:
* When the SRWD bit=1, and then FHWP/ACC is low (or FHWP/ACC is low before SRWD bit=1), it enters the
hardware protected mode. The data of the protected area is protected by the software protected mode by BP3, BP2, BP1, BP0 and the hardware protected mode by the FHWP/ACC against data modification. Note: to exit the hardware protected mode requires FHWP/ACC is driven high once the hardware protected mode is entered. If the FHWP/ACC pin is permanently connected high, the hardware protected mode can never be entered; only the software protected mode can be used via BP3, BP2, BP1, BP0. Protection Modes - HT82A6216 Internal Flash Memory
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CS must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as the Chip Select (FHCS#) goes high. The Write in Progress (WIP) bit can still be checked when the Write Status Register cycle is in progress. The WIP is set to 1 during the tW timing, and cleared 0 when the Write Status Register Cycle has completed, and the Write Enable Latch (WEL) bit is reset.
* Read Data Bytes - READ
byte is shifted out, so the whole memory can be read out with a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence to issue a READ instruction is: FHCS# goes low (R) sending READ instruction code (R) 3-byte address on SI (R) data out on SO (R) to end a READ operation, FHCS# going high can be used at any time during data out.
* Read Data Bytes at Higher Speed - FAST_READ
The read instruction is for reading data out. The address is latched on the rising edge of FHSCLK, and data shifts out on the falling edge of FHSCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each data
The FAST_READ instruction is to read data out quickly. The address is latched on the rising edge of SCLK, and each bit of data is shifted out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each data byte is shifted out, so the whole memory
FHCS#
FHSCLK
FHSI
FHSO
Read Data Bytes (READ) Sequence (Command 03)
FHCS#
FHSCLK
FHSI
FHSO
FHCS#
FHSCLK
FHSI
FHSO
Figure 4. Read at Higher Speed (FAST_READ) Sequence (Command 0B)
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can be read out with a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence to issue a FAST_READ instruction is: FHCS# goes low (R) sending FAST_READ instruction code (R) 3-byte address on SI (R) 1-dummy byte address on SI (R) data out on SO (R) to end FAST_READ operation can use FHCS# going high at any time durin g d a t a o u t . ( s e e Fi g u r e 4) W hi l e P r ogram/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.
* Sector Erase - SE
Write in Progress (WIP) bit can still be checked when a Sector Erase cycle is in progress. WIP is set to 1 during the tSE timing, and cleared to 0 when the Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP2, BP1, BP0 or BP3, BP2, BP1, BP0 bitts, the Sector Erase (SE) instruction will not be executed on the page.
* Block Erase - BE
The Sector Erase (SE) instruction is used to erase the data of the chosen sector to 1. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address in the sector (see Table 1 or Table 2) is a valid address for a Sector Erase (SE) instruction. CS must go high exactly at the byte boundary (when the latest eighth address byte has been latched-in); otherwise, the instruction will be rejected and not executed. Address bits [Am-A12] (Am is the most significant address) select the sector address. The sequence to issue a SE instruction is: FHCS# goes low (R) sending SE instruction code (R) 3-byte address on SI (R) FHCS# goes high. The self-timed Sector Erase Cycle time (tSE) is initiated as soon as the Chip Select (CS) goes high. The
FHCS#
The Block Erase (BE) instruction erases data of the chosen block to 1. A Write Enable (WREN) instruction must executed to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any addresses of the block (see Table 1 or Table 2) are valid addressed for a Block Erase (BE) instruction. CS must go high exactly at the byte boundary (when the latest eighth address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE instruction is: FHCS# goes low (R) sending BE instruction code (R) 3-byte address on SI (R) FHCS# goes high. The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (FHCS#) goes high. The Write in Progress (WIP) bit still can be checked out when the Sector Erase cycle is in progress. The WIP is set to 1 during the tBE timing, and cleared to 0 when the Sector Erase Cycle has completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP0~BP3 bits, the Block Erase (BE) instruction will not be executed on the page.
FHSCLK
FHSI
Note: SE command is 20(hex). Sector Erase (SE) Sequence (Command 20)
FHCS#
FHSCLK
FHSI
Note: BE command is 52 or D8(hex). Block Erase (BE) Sequence (Command 52 or D8) Rev. 1.10 28 October 30, 2009
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* Chip Erase - CE
The Chip Erase (CE) instruction is used to erase the data of the whole chip to 1. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the sector (see Table 1 or Table 2) is a valid address for the Chip Erase (CE) instruction. FHCS# must go high exactly at the byte boundary (when the latest eighth address byte has been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing CE instruction is: FHCS# goes low (R) sending CE instruction code (R) FHCS# goes high. (see Figure 5). The self-timed Chip Erase Cycle time (tCE) is initiated as soon as the Chip Select (FHCS#) goes high. The Write in Progress (WIP) bit still can be checked when the Chip Erase cycle is in progress. The WIP is set to 1 during the tCE timing, and cleared to 0 when the Chip Erase Cycle has completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected by the BP0~BP3 bits, the Chip Erase (CE) instruction will
not be executed. It will be only executed when BP0~BP3 are all set to 0.
* Page Program - PP
The Page Program (PP) instruction is used to programming the memory to 0. A Write Enable (WREN) instruction must executed to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). If the eighth least significant address bits (A7~A0) are not all 0, all transmitted data which goes beyond the end of the current page are programmed from the start address if the same page (from the address whose 8 least significant address bits (A7~A0) are all 0). FHCS# must go high exactly at the byte boundary (when the latest eighth address byte been latched-in); otherwise, the instruction will be rejected and not executed. If more than 256 bytes are sent to the device, the data of the last 256-bytes are programmed at the request page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at the request address of the page without effect on other address of the same page.
FHCS#
FHSCLK
FHSI
Note: CE command is 60(hex) or C7(hex). Figure 5. Chip Erase (CE) Sequence (Command 60 or C7)
FHCS#
FHSCLK
FHSI
FHCS#
FHSCLK
FHSI
Figure 6. Page Program (PP) Sequence (Command 02)
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The sequence to issue a PP instruction is: FHCS# goes low (R) sending PP instruction code (R) 3-byte address on SI (R) at least 1-byte on data on SI (R) FHCS# goes high (see Figure 6). The self-timed Page Program Cycle time(tPP) is initiated as soon as the Chip Select (FHCS#) goes high. The Write in Progress (WIP) bit still can still be checked when the Page Program cycle is in progress. WIP is set to 1 during the tPP timing, and cleared to 0 when the Page Program Cycle has completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by the BP0~BP3 bits, the Page Program (PP) instruction will not be executed.
* Deep Power-down - DP
struction to allow the ID been read out). During Power-down, the deep power-down mode automatically stops, and when powered-up, the device automatically is in standby mode. For the RDP instruction FHCS# must go high exactly at the byte boundary (when the latest eighth bit of the instruction code has been latched-in); otherwise, the instruction will not be executed. As soon as the Chip Select (FHCS#) goes high, a delay of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2.
* Release from Deep Power-down (RDP), Read Elec-
The Deep Power-down (DP) instruction is used to set the device to a condition of minimum power consumption. The standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to be executed. During the Deep Power-down mode, the device is not active and all Write/ Program/Erase instructions are ignored. When FHCS# goes high, it will only be in standby mode and not in deep power-down mode. The sequence to issue a DP instruction is: FHCS# goes low (R) sending DP instruction code (R) FHCS# goes high. (see Figure 7) Once the DP instruction is executed, all instructions will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction. (RES in-
tronic Signature (RES) The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (FHCS#) High. When Chip Select (FHCS#) is driven High, the device is put into the Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (FHCS#) must remain High for at least tRES2(max), as specified in the Table. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. The RES instruction reads out the old style of 8-bit Electronic Signature, whose values are shown in the table of ID Definitions. This is not the same as the RDID instruction. It is not recommended to use
FHCS#
FHSCLK
FHSI
Figure 7. Deep Power-down (DP) Sequence (Command B9)
FHCS#
FHSCLK
FHSI
FHSO
Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)
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FHCS#
FHSCLK
FHSI
FHSO
Figure 8. Release from Deep Power-down (RDP) Sequence (Command AB)
this for new designs. For new designs, use the RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, except when the device is in the program/erase/write cycle; here there is no effect on the current program/erase/write cycle in progress. The sequence is shown as figure 8. The RES instruction is ended when FHCS# goes high after the ID has been read out at least once. The ID outputs repeatedly if additional clock cycles on FHSCLK are repeatedly sent while FHCS# is low. If the device was not previously in the Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in the Deep Power-down mode, there is a delay of tRES2 to transition to the standby mode, and FHCS# must remain high for at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. The RDP instruction is to release the device from the Deep Power-down Mode.
* Read Electronic Manufacturer ID & Device ID (REMS)
shifting the instruction code 90h followed by two dummy bytes and one bytes address (A7~A0). After this, the Manufacturer ID for the device (C2h) and the Device ID are shifted out on the falling edge of FHSCLK with the most significant bit (MSB) first as shown in figure 9. The Device ID values are listed in the ID Definition table. If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving FHCS# high. Command Type HT82A6208 Internal Flash Memory Manufacture ID C2 RES 13 Manufacture ID REMS C2 13 Device ID Memory Type 20 Electronic ID Memory Density 14
RDID
- for the HT82A6208 internal Flash Memory The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initiated by driving the FHCS# pin low and
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FHCS#
FHSCLK
FHSI
FHSO
FHCS#
FHSCLK
FHSI
FHSO
Notes: ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first Figure 9. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90)
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* Read Electronic Manufacturer ID & Device ID
(REMS), (REMS2) - HT82A6216 internal Flash Memory The REMS & REMS2 instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The REMS & REMS2 instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initiated by driving the FHCS# pin low and shifting the instruction code 90H or EFh followed by two dummy bytes and one bytes address (A7~A0). After this, the Manufacturer ID for MXIC (C2h) and the Device ID are shifted out on the falling edge of FHSCLK with most significant bit (MSB) first as shown in figure 10. The Device ID values are listed in Table of ID Definitions. If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving FHCS# high.
Command Type RDID (JEDEC ID)
HT82A6216 Internal Flash Memory Manufacture ID C2 Memory Type 20 Electronic ID Memory Density 15
RES 14 Manufacture ID REMS/REMS2 C2 14 Device ID
FHCS#
FHSCLK
FHSI
FHSO
FHCS#
FHSCLK
FHSI
FHSO
Notes: ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first Figure 10. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90)
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FHCS# =VCC
FHCS# =VCC
FHSCLK
FHSCLK
FHSCLK
FHCS# =VCC
FHCS# =VCC
FHCS# =VCC
FHCS# =VCC
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FHCS# Active Setup Time (relative to FHSCLK) FHCS# Not Active Hold Time (relative to FHSCLK)
FHCS# Active Hold Time (relative to FHSCLK) FHCS# Not Active Setup Time (relative to FHSCLK) FHCS# Deselect Time
FHHOLD Setup Time (relative to FHSCLK) FHHOLD Hold Time (relative to FHSCLK) FHHOLD Setup Time (relative to FHSCLK) FHHOLD Hold Time (relative to FHSCLK) FHHOLD to Output Low-Z FHHOLD to Output High-Z
FHCS# High to Deep Power-down Mode FHCS# High to Standby Mode without Electronic Signature Read FHCS# High to Standby Mode with Electronic Signature Read
Figure 11. Maximum Negative Overshoot Waveform
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FHCS#
FHSCLK
FHSI
FHSO
Serial Input Timing
FHCS#
FHSCLK
FHSO
FHSI
Output Timing
FHCS#
FHSCLK
FHSO
FHHOLD
Hold Timing
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FHWP
FHCS#
FHSCLK
FHSI
FHSO
FHWP Disable Setup and Hold Timing during WRSR when SRWD=1
Power-up Timing
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Recommended Operating Conditions
At Device Power-Up AC timing illustrated in Figure 12 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly.
Figure 12. AC Timing at Device Power-Up
HT82A6208 Internal Flash Memory
HT82A6216 Internal Flash Memory
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Erase and Programming Performance
HT82A6208 Internal Flash Memory
HT82A6216 Internal Flash Memory
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Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high options for all ports and wake-up options on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. Depending upon which package is chosen, the microcontroller provides up to 32 bidirectional input/output lines labeled with port names PA, PB, PC and PD. These registers are mapped to the Data Memory with an addresses as shown in the Special Purpose Data Memory table. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction MOV A,[m], where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. The pull-high resistors are selectable via configuration options and are implemented using weak PMOS transistors. PA pins have bit select pull-high configuration options. Other ports have nibble select pull-high configuration options. Port Pin Wake-up If the HALT instruction is executed, the device will enter the Power Down Mode, where the system clock will stop resulting in power being conserved, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port pins from high to low. After a HALT instruction forces the microcontroller into entering the Power Down Mode, the processor will remain in a low-power state until the logic condition of the selected wake-up pin on the port pin changes from high to low. This function is especially suitable for applications that can be woken up via external switches. PA pins have bit select wake-up configuration options. Other ports have nibble select wake-up configuration options. All wake up the MCU on a high to low transition. This means if the pin is low, the I/O cannot wake-up the MCU. I/O Port Control Registers Each I/O port has its own control register PAC, PBC, PCC and PDC, to control the input/output configuration. With this control register, each CMOS output or input with or without pull-high resistor structures can be reconfigured dynamically under software control. Each of the I/O ports is directly mapped to a bit in its associated port control register. Note that PA pins can be setup to have NMOS outputs using configuration options. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a 1. This
V C o n tr o l B it Q D CK S Q P u ll- h ig h
DD
D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
D a ta B it Q D CK S Q M U X
W r ite D a ta R e g is te r
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PC0 PD0 PD1
/S C /S C /S D /S D /P W /P W /IN T /T M /A N /A N /T M ~PD
SA LKA IA OA M0 M1 R0 0 ~ P B 7 /A N 7 8 ~ P C 7 /A N 1 5 R1 7
PA4,PA5 PW M 0,PW M 1 M U X R e a d D a ta R e g is te r S y s te m W a k e -u p
EN (P W M 0 , P W M 1 ) W a k e - u p o p tio n
IN T fo r P A 6 o n ly T M R 0 o r T M R 1 fo r P A 7 o r P D 0 o n ly
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will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a 0, the I/O pin will be setup as an output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. Port B VDDIO Function The output drivers of most I/O pins use the VDD power supply line as their high voltage level. In this device pins PB0~PB6 can use a different voltage, other than VDD as their high level. This is supplied externally on pin PB7. This function is selected using configuration options. Pin-shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. For some pins, the chosen function of the multi-function I/O pins is set by configuration options while for others the function is set by application program control.
* External interrupt input * A/D inputs
These devices can have up to 16 A/D converter inputs depending upon which package type is chosen. All of these analog inputs are pin-shared with I/O pins on Port B and Port C. If these pins are to be used as A/D inputs and not as normal I/O pins then the corresponding bits in the A/D Converter Control Register, ADCR, must be properly set. There are no configuration options associated with the A/D function. If used as I/O pins, then full pull-high resistor configuration options remain, however if used as A/D inputs then any pull-high resistor options associated with these pins will be automatically disconnected. I/O Pin Structures The vast range of I/O functions and pin-shared options results in a huge variety of I/O pin structure types. For this reason the generic Input/Output Port diagram provided here is for general reference only. As the exact logical construction of the I/O pin will differ from the drawing, they are supplied as a guide only to assist with the functional understanding of the basic I/O pins. Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the data and port control register will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. If the PAC, PBC, PCC and PDC port control register, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated PA, PB, PC and PD port data registers are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct value into the port control register or by programming individual bits in the port control register using the SET [m].i and CLR [m].i instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports.
T1 S y s te m C lo c k T2 T3 T4 T1 T2 T3 T4
The external interrupt pin INT is pin-shared with the I/O pin PA6. For applications not requiring an external interrupt input, the pin-shared external interrupt pin can be used as a normal I/O pin, however to do this, the external interrupt enable bits in the INTC0 register must be disabled.
* External Timer Clock Inputs
The external timer pins TMR0 and TMR1 are pin-shared with I/O pins. To configure these pins to operate as timer inputs, the corresponding control bits in the timer control register must be correctly set. For applications that do not require external timer inputs, these pins can be used as normal I/O pins. Note that if used as normal I/O pins the timer mode control bits in the timer control register must select the timer mode, which has an internal clock source, to prevent the input pin from interfering with the timer operation.
* PWM outputs
P o rt D a ta
The device contains two PWM outputs which are pin-shared with I/O pins. The PWM output functions are chosen via configuration options and remain fixed after the device is programmed. Note that the corresponding bit of the port control register, PAC, must setup the pin as an output to enable the PWM output. If the PAC port control register has setup the pin as an input, then the pin will function as a normal logic input with the usual pull-high option, even if the PWM configuration option has been selected.
W r ite to P o r t
R e a d fro m
P o rt
Read/Write Timing The ports have the additional capability of providing wake-up functions. When the device is in the Power Down Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the port pins. Single or multiple pins on the ports can be setup to have this function.
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Timer/Event Counters
The provision of timers form an important part of any microcontroller giving the designer a means of carrying out time related functions. The device contains two internal 16-bit count-up timer which has three operating modes. The timer can be configured to operate as a general timer, external event counter or as a pulse width measurement device. The provision of an internal 16-stage prescaler on one of the timers clock circuitry gives added range to the timer. There are two types of registers related to the Timer/Event Counters. The first is the register that contain the actual value of the Timer/Event Counter and into which an initial value can be preloaded, and is known as TMR0H, TMR0L, TMR1H or TMR1L. Reading from this register retrieves the contents of the Timer/Event Counter. The second type of associated register is the Timer Control Register, which defines the timer options and determines how the Timer/Event Counter is to be used, and has the name TMR0C or TMR1C. This device can have the timer clocks configured to come from the internal clock sources. In addition, the timer clock sources can also be configured to come from the external timer pins. Configuring the Timer/Event Counter Input Clock Source The internal timers clock source can originate from a choice of internal system clocks or from an external clock source. The system clock input timer source is used when the timer is in the timer mode or in the pulse width measurement mode. The internal clock source of Timer1 passes trough a prescaler or can directly come from fsys/4 using bits T1S and T1PSS0/T1PSS1 in the MODE register. The prescaler clock source can come from either WDT OSC, RTC Oscillator or fSYS/4. The prescaler value is conditioned by the bits PS1C0, PS1C1 and PS1C2 in the TMR1C register. An external clock source is used when the timer is in the event counting mode, the clock source being provided on the shared TMR0 or TMR1 pin. Depending upon the condition of the T0E or T1E bit, each high to low, or low to high transition on the external timer pin will increment the counter by one. Timer Register - TMR0H/TMR1H, TMR0L/TMR1L The timer registers are special function registers located in the Special Purpose Data Memory and are the places where the actual timer values are stored. The timer registers are known as TMR0L, TMR0H, TMR1L and TMR1H. The value in the timer registers increases by one each time an internal clock pulse is received or an external transition occurs on the external timer pin. The timer will count from the initial value loaded by the preload register to the full count of FFFFH for the 16-bit timer at which point the timer overflows and an internal interrupt signal is generated. The timer value will then be reset with the initial preload register value and continue counting.
D a ta B u s L o w B y te B u ffe r T0M 1 fS TM R0 T0E
Y S /4
T0M 0 1 6 - B it P r e lo a d R e g is te r T0O N H ig h B y te L o w B y te O v e r flo w to In te rru p t R e lo a d
T im e r /E v e n t C o u n te r M o d e C o n tro l
1 6 - B it T im e r /E v e n t C o u n te r
16-bit Timer/Event Counter 0 Structure
D a ta B u s L o w B y te B u ffe r fS M U X 8 - s ta g e P r e s c a le r
YS
P S C IC 2 ~ P S C IC 0 /4 W DT OSC R T C O s c illa to r
YS
fS
/4 M
T1M 1 U X
T1M 0 1 6 - B it P r e lo a d R e g is te r T1O N H ig h B y te Low B y te O v e r flo w to In te rru p t R e lo a d
T im e r /E v e n t C o u n te r M o d e C o n tro l
T1PSS0 T1PSS1
T1S TM R1 T1E
1 6 - b it T im e r /E v e n t C o u n te r
16-bit Timer/Event Counter 1 Structure
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To achieve a maximum full range count of FFFFH, the preload registers must first be cleared to all zeros. It should be noted that after power-on, the preload register will be in an unknown condition. Note that if the Timer/Event Counter is switched off and data is written to its preload registers, this data will be immediately written into the actual timer registers. However, if the Timer/Event Counter is enabled and counting, any new data written into the preload data registers during this period will remain in the preload registers and will only be written into the timer registers the next time an overflow occurs. For 16-bit Timer/Event Counters which have both low byte and high byte timer registers, accessing these registers is carried out in a specific way. It must be note when using instructions to preload data into the low byte timer register, namely TMR1L, the data will only be placed in a low byte buffer and not directly into the low byte timer register. The actual transfer of the data into the low byte timer register is only carried out when a write to its associated high byte timer register, namely TMR1H, is executed. On the other hand, using instructions to preload data into the high byte timer register will result in the data being directly written to the high byte timer register. At the same time the data in the low byte buffer will be transferred into its associated low byte timer register. For this reason, the low byte timer register should be written first when preloading data into the 16-bit timer registers. It must also be noted that to read the contents of the low byte timer register, a read to the high byte timer register must be executed first to latch the contents of the low byte timer register into its associated low byte buffer. After this has been done, the low byte timer register can be read in the normal way. Note that reading the low byte timer register will result in reading the previously latched contents of the low byte buffer and not the actual contents of the low byte timer register. Timer Control Register - TMR0C/TMR1C The flexible features of the Holtek microcontroller Timer/Event Counters enable them to operate in three different modes, the options of which are determined by the contents of the Timer Control Register TMR0C/ TMR1C. Together with the TMR0L/TMR1L and TMR0H/ TMR1H registers, these three registers control the full operation of the Timer/Event Counter. Before the timer can be used, it is essential that the TMR0C/TMR1C register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialisation. To choose which of the three modes the timer is to operate in, the timer mode, the event counting mode or the pulse width measurement mode, bits T0M0/T1M0 and T0M1/T1M1 must be set to the required logic levels. The timer-on bit T0ON/T1ON or bit 4 of the TMR0C/TMR1C register provides the basic on/off control of the timer, setting the bit high allows the counter to run, clearing the bit stops the counter. If the timer is in the event count or pulse width measurement mode the active transition edge level type is selected by the logic level of the T0E/T1E or bit 3 of the TMR0C/TMR1C register. Configuring the Timer Mode In this mode, the Timer/Event Counter can be utilised to measure fixed time intervals, providing an internal interrupt signal each time the Timer/Event Counter overflows. To operate in this mode, the Operating Mode Select bit pair, T0M1/T0M0 or T1M1/T1M0, in the Timer Control Register must be set to the correct value as shown. Control Register Operating Mode Select Bits for the Timer Mode Bit7 Bit6 1 0
In this mode the internal clock, fSYS/4 is used as the internal clock for the Timer/Event Counter. After the other bits in the Timer Control Register have been setup, the enable bit T0ON or T1ON, which is bit 4 of the Timer Control Register, can be set high to enable the Timer/Event Counter to run. Each time an internal clock cycle occurs, the Timer/Event Counter increments by one. When it is full and overflows, an interrupt signal is generated and the Timer/Event Counter will reload the value already loaded into the preload register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit in the Interrupt Control Register, INTC, is reset to zero.
P r e s c a le r O u tp u t
In c re m e n t T im e r C o n tr o lle r
T im e r + 1
T im e r + 2
T im e r + N
T im e r + N + 1
Timer Mode Timing Chart
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b7 T0M 1 b0 T0M 0 T0O N T0E TM R0C R e g is te r
N o t im p le m e n te d , r e a d a s " 0 "
E v e n t C o u n te r a c tiv e e d g e s e le c t 1 : c o u n t o n fa llin g e d g e 0 : c o u n t o n r is in g e d g e T im e r /E v e n t C o u n te r c o u n tin g e n a b le 1 : e n a b le 0 : d is a b le N o t im p le m e n te d , r e a d a s " 0 " O p e r a tin T0M 1 T 0 0 1 1 g m ode s 0M 0 no 0 ev 1 tim 0 1 pu e le c t m od entc erm ls e w e a v a ila b le o u n te r m o d e ode id th m e a s u r e m e n t m o d e
Timer/Event Counter 0 Control Register
b7 T1M 1 T1M 0 T1O N T1E PS1C2 PS1C1 b0 PS1C0 TM R1C R e g is te r
T im e r p r e s c a le r r a te s e le c t PS1C2 PS1C 1 PS1C 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Ev 1: 0: Pu 1: 0: entC coun coun ls e W s ta rt s ta rt o u n te r a c tiv e e d g t o n fa llin g e d g e t o n r is in g e d g e id th M e a s u r e m e n c o u n tin g o n r is in g c o u n tin g o n fa llin g
fS P = fS fS P = fS fS P = fS fS P = fS fS P = fS fS P = fS fS P = fS fS P = fS
/3 2 /6 4 /1 2 /2 5 /5 1 /1 0 /2 0 /4 0 8 6 2
24 48 96
e s e le c t t a c tiv e e d g e s e le c t e d g e , s to p o n fa llin g e d g e e d g e , s to p o n r is in g e d g e
T im e r /E v e n t C o u n te r c o u n tin g e n a b le 1 : e n a b le 0 : d is a b le N o t im p le m e n te d , r e a d a s " 0 " O p e r a tin g T1M 1 T 0 0 1 1 m o d e s e le 1M 0 0 no 1 ev 0 tim 1 pu ct m od entc erm ls e w e a v a ila b le o u n te r m o d e ode id th m e a s u r e m e n t m o d e
Timer/Event Counter 1 Control Register
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Configuring the Event Counter Mode In this mode, a number of externally changing logic events, occurring on the external timer pin, can be recorded by the Timer/Event Counter. To operate in this mode, the Operating Mode Select bit pair, T0M1/T0M0 or T1M1/T1M0, in the Timer Control Register must be set to the correct value as shown. Control Register Operating Mode Select Bits for the Event Counter Mode Bit7 Bit6 0 1 As a result when the timer overflows it will generate a timer interrupt and corresponding wake-up source. Configuring the Pulse Width Measurement Mode In this mode, the Timer/Event Counter can be utilised to measure the width of external pulses applied to the external timer pin. To operate in this mode, the Operating Mode Select bit pair, T0M1/T0M0 or T1M1/T1M0, in the Timer Control Register must be set to the correct value as shown. Control Register Operating Mode Select Bits for the Pulse Width Measurement Mode Bit7 Bit6 1 1
In this mode, the external timer pin, TMR0 or TMR1, is used as the Timer/Event Counter clock source, however it is not divided by the internal prescaler. After the other bits in the Timer Control Register have been setup, the enable bit T0ON or T1ON, which is bit 4 of the Timer Control Register, can be set high to enable the Timer/Event Counter to run. If the Active Edge Select bit T0E or T1E, which is bit 3 of the Timer Control Register, is low, the Timer/Event Counter will increment each time the external timer pin receives a low to high transition. If the Active Edge Select bit is high, the counter will increment each time the external timer pin receives a high to low transition. When it is full and overflows, an interrupt signal is generated and the Timer/Event Counter will reload the value already loaded into the preload register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit in the Interrupt Control Register, INTC, is reset to zero. As the external timer pin is an independent pin and not shared with an I/O pin, the only thing to ensure the timer operate as an event counter is to ensure that the Operating Mode Select bits in the Timer Control Register place the Timer/Event Counter in the Event Counting Mode. It should be noted that in the event counting mode, even if the microcontroller is in the Power Down Mode, the Timer/Event Counter will continue to record externally changing logic events on the timer input pin.
E x te rn a l E v e n t In c re m e n t T im e r C o u n te r
In this mode the internal clock, fSYS/4 is used as the internal clock for the 16-bit Timer/Event Counter 0. The T1S and T1PSS0/T1PSS1 bits select the internal clock for the 16-bit Timer/Event Counter 1. After the other bits in the Timer Control Register have been setup, the enable bit T0ON or T1ON, which is bit 4 of the Timer Control Register, can be set high to enable the Timer/Event Counter, however it will not actually start counting until an active edge is received on the external timer pin. If the Active Edge Select bit T0E or T1E, which is bit 3 of the Timer Control Register, is low, once a high to low transition has been received on the external timer pin, TMR0 or TMR1, the Timer/Event Counter will start counting until the external timer pin returns to its original high level. At this point the enable bit will be automatically reset to zero and the Timer/Event Counter will stop counting. If the Active Edge Select bit is high, the Timer/Event Counter will begin counting once a low to high transition has been received on the external timer pin and stop counting when the external timer pin returns to its original low level. As before, the enable bit will be automatically reset to zero and the Timer/Event Counter will stop counting. It is important to note that in the Pulse Width Measurement Mode, the enable bit is
T im e r + 1
T im e r + 2
T im e r + 3
Event Counter Mode Timing Chart
E x te r n a l T im e r P in In p u t T0O N orT1O N ( w ith T 0 E o r T 1 E = 0 ) P r e s c a le r O u tp u t In c re m e n t T im e r C o u n te r T im e r +1 +2 +3 +4
P r e s c a le r O u tp u t is s a m p le d a t e v e r y fa llin g e d g e o f T 1 .
Pulse Width Measure Mode Timing Chart Rev. 1.10 45 October 30, 2009
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automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the enable bit can only be reset to zero under program control. The residual value in the Timer/Event Counter, which can now be read by the program, therefore represents the length of the pulse received on the external timer pin. As the enable bit has now been reset, any further transitions on the external timer pin will be ignored. Not until the enable bit is again set high by the program can the timer begin further pulse width measurements. In this way, single shot pulse measurements can be easily made. It should be noted that in this mode the Timer/Event Counter is controlled by logical transitions on the external timer pin and not by the logic level. When the Timer/Event Counter is full and overflows, an interrupt signal is generated and the Timer/Event Counter will reload the value already loaded into the preload register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit in the Interrupt Control Register, INTC, is reset to zero. As the external timer pin is an independent pin and not shared with an I/O pin, the only thing to ensure the timer operate in Pulse Width Measurement mode is to ensure that the Operating Mode Select bits in the Timer Control Register place the Timer/Event Counter in the Pulse Width Measurement Mode. Prescaler Bits PS1C0~PS1C2 of the TMR1C register are used to define the pre-scaling stages of the internal clock source of the Timer/Event Counter 1. I/O Interfacing The Timer/Event Counter, when configured to run in the event counter or pulse width measurement mode, require the use of external pins for correct operation. As these pins are shared pins they must be configured correctly to ensure they are setup for use as Timer/Event Counter inputs and not as a normal I/O pins. This is implemented by ensuring that the mode select bits in the Timer/Event Counter control register, select either the event counter or pulse width measurement mode. Additionally the relevant Port Control Register for this pin must be set high to ensure that the pin is setup as an input. Any pull-high resistor configuration option on this pin will remain valid even if the pin is used as a Timer/Event Counter input. Programming Considerations When configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller. In this mode when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector. For the pulse width measurement mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. As this is an external event and not synchronised with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. As a result, there may be small differences in measured values requiring programmers to take this into account during programming. The same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronised with the internal system or timer clock. When the Timer/Event Counter is read, or if data is written to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. Care must be taken to ensure that the timers are properly initialised before using them for the first time. The associated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. The edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. It is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are unknown. After the timer has been initialised the timer can be turned on and off by controlling the enable bit in the timer control register. Note that setting the timer enable bit high to turn the timer on, should only be executed after the timer mode bits have been properly setup. Setting the timer enable bit high together with a mode bit modification, may lead to improper timer operation if executed as a single timer control register byte write instruction.
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When the Timer/Event counter overflows, its corresponding interrupt request flag in the interrupt control register will be set. If the timer interrupt is enabled this will in turn generate an interrupt signal. However irrespective of whether the interrupts are enabled or not, a Timer/Event counter overflow will also generate a wake-up signal if the device is in a Power-down condition. This situation may occur if the Timer/Event Counter is in the Event Counting Mode and if the external signal continues to change state. In such a case, the Timer/Event Counter will continue to count these external events and if an overflow occurs the device will be woken up from its Power-down condition. To prevent such a wake-up from occurring, the timer interrupt request flag should first be set high before issuing the HALT instruction to enter the Power Down Mode. Timer Program Example This program example shows how the Timer/Event Counter registers are setup, along with how the interrupts are enabled and managed. Note how the Timer/Event Counter is turned on, by setting bit 4 of the Timer Control Register. The Timer/Event Counter can be turned off in a similar way by clearing the same bit. This example program sets the Timer/Event Counter to be in the timer mode, which uses the internal system clock as the clock source.
org 04h ; USB interrupt vector reti org 0ch ; Timer/Event Counter 0 interrupt vector jmp tmrint ; jump here when Timer overflows : org 20h ; main program ;internal Timer/Event Counter 0 interrupt routine tmrint: : ; Timer/Event Counter main program placed here : reti : : begin: ;setup Timer registers mov a,09bh ; setup Timer preload value mov tmr0l,a; Mov a,0ffh ; setup Timer preload value Mov trm0h,a mov a,080h ; setup Timer control register mov tmr0c,a ; timer mode ; setup interrupt register mov a,009h ; enable master interrupt and timer interrupt mov intc0,a set tmr0c.4 ; start Timer/Event Counter - note mode bits must be previously setup
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Interrupts
Interrupts are an important part of any microcontroller system. When an external interrupt pin transition or an internal function such as a Timer/Event Counter overflow, an USB interrupt, or transmission or reception of SPI data occurs, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. Each device contains two external interrupts and several internal interrupts functions. The external interrupt is controlled by the action of the external interrupt pins, while the internal interrupts are controlled by the Timer/Event Counter overflow, a USB interrupt and SPI data transmission or reception. Interrupt Registers Overall interrupt control, which means interrupt enabling and request flag setting, is controlled by the two interrupt control registers, which are located in the Data Memory. By controlling the appropriate enable bits in these registers each individual interrupt can be enabled or disabled. Also when an interrupt occurs, the corresponding request flag will be set by the microcontroller. The global enable flag if cleared to zero will disable all interrupts. Interrupt Operation A USB interrupt , a Timer/Event Counter overflow, 8-bits of data transmission or reception on either of the SPI interfaces or an active edge on external interrupt pin will all generate an interrupt request by setting their corresponding request flag, if their appropriate interrupt enable bit is set. When this happens, the Program Counter, which stores the address of the next instruction
A u to m a tic a lly C le a r e d b y IS R M a n u a lly S e t o r C le a r e d b y S o ftw a r e U S B In te rru p t R e q u e s t F la g U S B F _ A E x te rn a l In te rru p t R e q u e s t F la g E IF T im e r /E v e n t C o u n te r 0 O v e r flo w In te r r u p t R e q u e s t F la g T F 0 S P I_ A In te rru p t R e q u e s t F la g S IF _ A S P I_ B In te rru p t R e q u e s t F la g S IF _ B T im e r /E v e n t C o u n te r 1 O v e r flo w In te r r u p t R e q u e s t F la g T F 1 EUI
to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a JMP statement which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a RETI statement, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagram with their order of priority. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full.
A u to m a tic a lly D is a b le d b y IS R C a n b e E n a b le d M a n u a lly P r io r ity EMI H ig h
EEI
E T I0 E S II_ A In te rru p t P o llin g
E S II_ B
E T I1
Low
Interrupt Structure
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b7 TF0 E IF USBF E T I0 EEI EUI b0 EMI IN T C 0 R e g is te r M a s te r in te r r u p t g lo b a l e n a b le 1 : g lo b a l e n a b le 0 : g lo b a l d is a b le U S B in te r r u p t e n a b le 1 : e n a b le 0 : d is a b le E x te r n a l in te r r u p t e n a b le 1 : e n a b le 0 : d is a b le T im e r /E v e n t C o u n te r 0 1 : e n a b le 0 : d is a b le in te r r u p t e n a b le
U S B in te r r u p t r e q u e s t fla g 1 : a c tiv e 0 : in a c tiv e E x te r n a l in te r r u p t r e q u e s t fla g 1 : a c tiv e 0 : in a c tiv e T im e r /E v e n t C o u n te r 0 in te r r u p t r e q u e s t fla g 1 : a c tiv e 0 : in a c tiv e F o r te s t m o d e u s e d o n ly M u s t b e w r itte n a s " 0 " ; o th e r w is e m a y r e s u lt in u n p r e d ic ta b le o p e r a tio n
INTC0 Register
b7 TF1 S IF _ B S IF _ A E E I1 E S II_ B
b0 E S II_ A IN T C 1 R e g is te r S P I S e r ia l In te r fa c e A in te r r u p t e n a b le 1 : e n a b le 0 : d is a b le S P I S e r ia l In te r fa c e B in te r r u p t e n a b le 1 : e n a b le 0 : d is a b le T im e r /E v e n t C o u n te r 1 in te r r u p t e n a b le 1 : e n a b le 0 : d is a b le N o t im p le m e n te d , r e a d a s " 0 " S P I S e r ia l in te r fa c e A d a ta tr a n s fe r r e d o r d a ta r e c e iv e d in te r r u p t r e q u e s t fla g 1 : a c tiv e 0 : in a c tiv e S P I S e r ia l in te r fa c e B d a ta tr a n s fe r r e d o r d a ta r e c e iv e d in te r r u p t r e q u e s t fla g 1 : a c tiv e 0 : in a c tiv e T im e r /E v e n t C o u n te r 1 in te r r u p t r e q u e s t fla g 1 : a c tiv e 0 : in a c tiv e N o t im p le m e n te d , r e a d a s " 0 "
INTC1 Register
Rev. 1.10
49
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
Interrupt Priority Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of simultaneous requests, the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source USB Interrupt External Interrupt Timer/Event Counter 0 Overflow Interrupt SPI_A Interrupt SPI_B Interrupt Timer/Event Counter 1 Overflow Interrupt Priority 1 2 3 4 5 6 Vector 0004H 0008H 000CH 0010H 0014H 0018H vector at location 0CH or 018H, will take place. When the interrupt is serviced, the timer interrupt request flag, TF0 or TF1, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. SPI Interrupt For an SPI Interrupt to occur, the global interrupt enable bit, EMI, and the corresponding SPI interrupt enable bit, ESII_A or ESII_B, must be first set. An actual SPI Interrupt will take place when one of the two SPI interrupt request flags, SIF_A or SIF_B, are set, a situation that will occur when 8-bits of data are transferred or received from either of the SPI interfaces. When the interrupt is enabled, the stack is not full and an SPI_A interrupt occurs, a subroutine call to the SPI_A interrupt vector at location 10H, will take place. For an SPI_B interrupt, a subroutine call to the SPI_B interrupt vector at location 14H, will take place. When the interrupt is serviced, the SPI interrupt request flag, SIF_A or SIF_B, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. USB Interrupt A USB interrupts will be triggered by the following USB events, at which point the the related interrupt request flag, USBF in the INTC0 register, will be set.
* Accessing the corresponding USB FIFO from the PC * A USB suspend signal from the PC * A USB resume signal from the PC * A USB Reset signal
Suitable masking of the individual interrupts using the interrupt registers can prevent simultaneous occurrences. External Interrupt For an external interrupt to occur, the global interrupt enable bit, EMI, and external interrupt enable bit, EEI, must first be set. An actual external interrupt will take place when the external interrupt request flag, EIF is set, a situation that will occur when a high to low transition appears on the interrupt pins. The external interrupt pin is pin-shared with the I/O pins PA6 can only be configured as an external interrupt pin if the corresponding external interrupt enable bits in the interrupt control register INTC0 have been set. The pins must also be setup as inputs by setting the corresponding PAC.6 bits in the port control register. When the interrupt is enabled, the stack is not full and a high to low transition appears on the external interrupt pin, a subroutine call to the external interrupt vector at location 08H will take place. When the interrupt is serviced, the external interrupt request flag, EIF will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor configuration options on these pins will remain valid even if the pins are used as external interrupt inputs. Timer/Event Counter Interrupt For a Timer/Event Counter interrupt to occur, the global interrupt enable bit, EMI, and the corresponding timer interrupt enable bit, ETI0 or ETI1, must first be set. An actual Timer/Event Counter interrupt will take place when the Timer/Event Counter interrupt request flag, TF0 or TF1, is set, a situation that will occur when the Timer/Event Counter overflows. When the interrupt is enabled, the stack is not full and a Timer/Event Counter overflow occurs, a subroutine call to the timer interrupt
When the interrupt is enabled, the stack is not full and the USB interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag, USBF, and the EMI bit will be cleared to disable other interrupts. When PC Host accesses the FIFO of the device, the corresponding request USR bit is set, and a USB interrupt is triggered. Therefore it can be determined which FIFO has been accessed. When the interrupt has been served, the corresponding bit should be cleared by the program. When the device receive a USB Suspend signal from the Host PC, the suspend line, bit0 of USC, is set and a USB interrupt is also triggered. Also when device receive a Resume signal from the Host PC, the resume line, bit3 of USC, is set and a USB interrupt is triggered. Programming Considerations By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt control register until the corresponding interrupt is serviced or until the request flag is cleared by a software instruction.
Rev. 1.10
50
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
It is recommended that programs do not use the CALL subroutine instruction within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. All of these interrupts have the capability of waking up the processor when in the Power Down Mode. Only the Program Counter is pushed onto the stack. If the contents of the accumulator or status register are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents should be saved in advance. one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing a proper reset operation. In such cases it is recommended that an external RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be inhibited. After the RES line reaches a certain voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the microcontroller will begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer.
VDD RES S S T T im e - o u t In te rn a l R e s e t 0 .9 V tR
DD
Reset and Initialisation
A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. One example of this is where after power has been applied and the microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are five ways in which a microcontroller reset can occur, through events occurring both internally and externally:
* Power-on Reset
STD
Power-On Reset Timing Chart For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference.
VDD 100kW RES 0 .1 m F VSS
Basic Reset Circuit For applications that operate within an environment where more noise is present the Enhanced Reset Circuit shown is recommended.
0 .0 1 m F 100kW RES
10kW
VDD
0 .1 m F VSS
Enhanced Reset Circuit More information regarding external reset circuits is located in Application Note HA0075E on the Holtek website. 51 October 30, 2009
The most fundamental and unavoidable reset is the Rev. 1.10
HT82A623R/HT82A6208/HT82A6216
* RES Pin Reset * Watchdog Time-out Reset during Power Down
This type of reset occurs when the microcontroller is already running and the RES pin is forcefully pulled low by external hardware such as an external switch. In this case as in the case of other reset, the Program Counter will reset to zero and program execution initiated from this point. Note that as the external reset pin is also pin-shared with PA7, if it is to be used as a reset pin, the correct reset configuration option must be selected.
RES S S T T im e - o u t In te rn a l R e s e t 0 .4 V 0 .9 V
DD DD
The Watchdog time-out Reset during Power Down is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to 0 and the TO flag will be set to 1. Refer to the A.C. Characteristics for tSST details.
W D T T im e - o u t
tS
S S T T im e - o u t
ST
tR
STD
WDT Time-out Reset during Power Down Timing Chart Reset Initial Conditions
RES Reset Timing Chart
* Low Voltage Reset - LVR
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is selected via a configuration option. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for a time greater than that specified by tLVR in the A.C. characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. The actual VLVR value can be selected via configuration options.
LVR tR S S T T im e - o u t In te rn a l R e s e t
STD
The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the Power Down function or Watchdog Timer. The reset flags are shown in the table: TO PDF 0 0 0 1 1 0 0 0 u 1 RESET Conditions RES reset during power-on RES wake-up during Power Down RES or LVR reset during normal operation WDT time-out reset during normal operation WDT time-out reset during Power Down
Note: u stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Program Counter Condition After RESET Reset to zero All interrupts will be disabled Clear after reset, WDT begins counting Timer Counter will be turned off The Timer Counter Prescaler will be cleared
Low Voltage Reset Timing Chart
* Watchdog Time-out Reset during Normal Operation
Interrupts WDT Timer/Event Counter Prescaler
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except that the Watchdog time-out flag TO will be set to 1.
W D T T im e - o u t
tR
S S T T im e - o u t In te rn a l R e s e t
STD
Input/Output Ports I/O ports will be setup as inputs WDT Time-out Reset during Normal Operation Timing Chart Stack Pointer Stack Pointer will point to the top of the stack
Rev. 1.10
52
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects the microcontroller internal registers. Register MP0 MP1 ACC PCL TBLP TBLH WDTS STATUS INTC0 TMR1H TMR1L TMR1C TMR0H TMR0L TMR0C PA PAC PB PBC PC PCC PD PDC USB_STAT UINT INTC1 TBHP USC USR UCC AWR STALL SIES MISC UFIEN FIFO0 Reset (Power-on) xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx ---- -111 --00 xxxx 0000 0000 xxxx xxxx xxxx xxxx 00-0 1--xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 --xx 0000 0000 1111 -000 -000 xxxx xxxx 1000 0000 ---- 0000 0000 0000 0000 0000 ---- 0000 00-0 0000 0000 0000 ---- 0000 xxxx xxxx WDT Time-out (Normal Operation) xxxx xxxx xxxx xxxx uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu ---- -111 --1u uuuu 0000 0000 xxxx xxxx xxxx xxxx 00-0 1--xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 --xx 0000 0000 uuuu -000 -000 uuuu uuuu uuuu xuux ---- uuuu uuuu uuuu uuuu uuuu ---- uuuu uu-x xuuu xxuu uuuu ---- uuuu xxxx xxxx RES Reset (Normal Operation) xxxx xxxx xxxx xxxx uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu ---- -111 --00 uuuu 0000 0000 xxxx xxxx xxxx xxxx 00-0 1--xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 --xx 0000 0000 1111 -000 -000 uuuu uuuu 1000 0000 ---- 0000 0000 0000 0000 0000 ---- 0000 00-0 0000 0000 0000 ---- 0000 xxxx xxxx RES Reset (HALT) xxxx xxxx xxxx xxxx uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu ---- -111 --00 uuuu 0000 0000 xxxx xxxx xxxx xxxx 00-0 1--xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 --xx 0000 0000 1111 -000 -000 uuuu uuuu 1000 0000 ---- 0000 0000 0000 0000 0000 ---- 0000 00-0 0000 0000 0000 ---- 0000 xxxx xxxx WDT Time-out (HALT)* uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu ---- -111 --11 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu-u u--uuuu uuuu uuuu uuuu uu-u u--uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --xx 0000 0000 uuuu -uuu -uuu uuuu uuuu uuuu xuux ---- uuuu uuuu uuuu uuuu uuuu ---- uuuu uu-x uuuu xxuu uuuu ---- uuuu xxxx xxxx USB Reset (Normal) xxxx xxxx xxxx xxxx uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu ---- -111 --uu uuuu 0000 0000 uuuu uuuu uuuu uuuu uu-u u--xxxx xxxx xxxx xxxx uu-u u--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 --xx 0000 0000 1111 -000 -000 uuuu uuuu 1uuu 0100 ---- 0000 0uu0 u000 0000 0000 ---- 0000 00-0 0000 0000 0000 ---- 0000 xxxx xxxx USB Reset (HALT) xxxx xxxx xxxx xxxx uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu ---- -uuu --01 uuuu 0000 0000 uuuu uuuu uuuu uuuu uu-u u--xxxx xxxx xxxx xxxx uu-u u--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 --xx 0000 0000 1111 -000 -000 uuuu uuuu 1uuu 0100 ---- 0000 0uu0 u000 0000 0000 ---- 0000 00-0 0000 0000 0000 ---- 0000 xxxx xxxx
Rev. 1.10
53
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
Reset (Power-on) xxxx xxxx xxxx xxxx xxxx xxxx ---- 0000 0000 0000 0110 0000 uuuu uuuu xxxx ---xxxx xxxx 0100 0000 0--- --00 0110 0000 uuuu uuuu xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 WDT Time-out (Normal Operation) xxxx xxxx xxxx xxxx xxxx xxxx ---- uuuu uuuu uuuu 0110 0000 uuuu uuuu xxxx ---xxxx xxxx 0100 0000 0--- --00 0110 0000 uuuu uuuu xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 RES Reset (Normal Operation) xxxx xxxx xxxx xxxx xxxx xxxx ---- 0000 0000 0000 0110 0000 uuuu uuuu xxxx ---xxxx xxxx 0100 0000 0--- --00 0110 0000 uuuu uuuu xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 RES Reset (HALT) xxxx xxxx xxxx xxxx xxxx xxxx ---- 0000 0000 0000 0110 0000 uuuu uuuu xxxx ---uuuu uuuu 0100 0000 ---- --00 0110 0000 uuuu uuuu xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 WDT Time-out (HALT)* xxxx xxxx xxxx xxxx xxxx xxxx ---- uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---uuuu uuuu uuuu uuuu u--- --uu uuuu uuuu uuuu uuuu xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu USB Reset (Normal) xxxx xxxx xxxx xxxx xxxx xxxx ---- 0000 0000 0000 uuuu uuuu uuuu uuuu xxxx ---xxxx xxxx 0100 0000 1--- --00 uuuu uuuu uuuu uuuu xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 USB Reset (HALT) xxxx xxxx xxxx xxxx xxxx xxxx ---- 0000 0000 0000 uuuu uuuu uuuu uuuu xxxx ---xxxx xxxx 0100 0000 ---- --00 uuuu uuuu uuuu uuuu xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Register FIFO1 FIFO2 FIFO3 UFOEN UFC0 SBCRA SBDRA ADRL ADRH ADCR ACSR SBCRB SBDRB MODE SPI_REG PWMBR0 PWM0DR PWMBR1 PWM1DR PWMCTL Note:
* means warm reset, - not implemented u means unchanged, x means unknown
Rev. 1.10
54
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
Oscillator
These devices provide two types of system oscillator circuits, an 6MHz or 12MHz crystal oscillator and a 32768Hz crystal oscillator, the choice of which is determined by software. To use the 6MHz or 12MHz oscillator, a suitable crystal is connected between OSC1 and OSC2. It is a default option at IC power-on. The other oscillator circuit is designed for the real time clock. For this device, only a 32768Hz crystal oscillator can be used. The crystal should be connected between OSC3 and OSC4. This oscillator is designed for system clocks. The Power-down mode stops the system oscillator to conserve power.
OSC1
OSC3
OSC4
Crystal/Ceramic Oscillator
Watchdog Timer Oscillator The WDT oscillator is a fully self-contained free running on-chip RC oscillator with a typical period of 65ms at 5V requiring no external components. When the device enters the Power Down Mode, the system clock will stop running but the WDT oscillator continues to free-run and to keep the watchdog active. However, to preserve power in certain applications the WDT oscillator can be disabled via a configuration option. Operation Mode The device supports two system clocks: a high frequency system clock (6MHz, 12MHz) or a low system clock, 32768Hz. There is a single register that determines how to define which system mode is in operation. The system clock is changed as shown in the following procedure. From high frequency to low frequency:
* Set MODS to 1 * Wait a delay time - 400ms if the 32K oscillator is off, no
OSC2
Crystal Oscillator A crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator. No other external components are required. In stead of a crystal, a resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 may be required. The devices can operate only with 6MHz or 12MHz system clocks. In order to ensure that the USB SIE functions properly, users should correctly configure the SCLKSEL bit of the SCC Register. The default system clock is 12MHz. RTC Oscillator When the device enter a Power-down condition, the internal clocks are normally switched off to stop microcontroller activity and to conserve power. However, in many microcontroller applications it may be necessary to keep some internal functions operational, such as timers, even when the microcontroller is in the Power-down mode. To provide this feature, this device incorporates an RTC oscillator, which will remain active at all times, even when the microcontroller is in the power down condition. This clock source has a fixed frequency of 32768Hz and requires a 32768Hz crystal to be connected between pins OSC3 and OSC4. The RTC oscillator circuit enable/disable is controlled by the F32K_dis bit in the MODE register. An additional bit F32K_CTRL enables the RTC oscillator to be powered up quickly.
delay if the if the 32K oscillator is on
* The MCU will switch to the low frequency 32768Hz
oscillator and turn-off the high frequency system clock From low frequency to high frequency:
* Set Hfreq_en to 1 to turn-on the high frequency os-
cillator
* Wait a delay time to make sure that the high frequency
oscillator is stable - 5ms
* Set MODS to 0 * The MCU will switch to the high frequency oscillator
but the 32768Hz oscillator will continue to oscillate.
Low Speed O p e r a tio n M O DE=1 H fre q = 0
S e t H fre q to "1 " D e la y fo r c lo c k to s ta b ilis e C le a r M O D S to " 0 "
H ig h S p e e d O p e r a tio n M O DE=0 H fre q = 1
S e t M O D S to "1 " D e la y is 3 2 K o s c illa to r O ff H fr e q a u to c le a r e d to " 0 "
Mode Switching
Rev. 1.10
55
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
Bit No. 0 Label MODS Function High/Low frequency system clock select bit 0: High frequency system clock - 6MHz or 12MHz select - default 1: 32768Hz system clock select 1: Enable High frequency system clock, hardware will automatically clear this bit when MODS switches from low to high 1: Disable 32768Hz oscillator - default enable 0: Enable 32768Hz oscillator 1: VDD < 2.2V 0: VDD > 2.2V Timer/Event Counter 1 clock source select 00: RTC (default) 01: fSYS/4 10: WDT OSC 11: no source Timer/Event Counter 1 clock source select 0: fSYS/4 (default) 1: Timer1 Prescaler output RTC oscillator quick start function 1: Quick start enabled 0: Quick start disabled - lower operating current This bit will set by the hardware during power on, once the 32K oscillator is stable the bit can be cleared by the application program to reduce power consumption. MODE (40H) Register
1 2 3
Hfreq_en F32K_dis 2.2LVD
4 5
T1PSS0 T1PSS1
6
T1S
7
F32K_ctrl
Power Down Mode and Wake-up
Power Down Mode All of the Holtek microcontrollers have the ability to enter a Power Down Mode. When the device enters this mode, the normal operating current, will be reduced to an extremely low standby current level. This occurs because when the device enters the Power Down Mode, the system oscillator is stopped which reduces the power consumption to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requiring a full reset. This feature is extremely important in application areas where the microcontroller must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. Entering the Power Down Mode There is only one way for the device to enter the Power Down Mode and that is to execute the HALT instruction in the application program. When this instruction is executed, the following will occur:
* The system oscillator will stop running and the appli* The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the WDT or RTC oscillator. The WDT will stop if its clock source originates from the system clock.
* The I/O ports will maintain their present condition. * In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the Power Down Mode is to keep the current consumption of the microcontroller to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs.
cation program will stop at the HALT instruction.
* If the RTC oscillator configuration option is enabled
then the RTC clock will keep running.
* The Data Memory contents and registers will maintain
their present condition. Rev. 1.10 56 October 30, 2009
HT82A623R/HT82A6208/HT82A6216
If the configuration options have enabled the Watchdog Timer internal oscillator then this will continue to run when in the Power Down Mode and will thus consume some power. For power sensitive applications it may be therefore preferable to use the system clock source for the Watchdog Timer. If any I/O pins are configured as A/D analog inputs using the channel configuration bits in the ADCR register, then the A/D converter will be turned on and a certain amount of power will be consumed. It may be therefore desirable before entering te Power Down Mode to ensure that the A/D converter is powered down by ensuring that any A/D input pins are setup as normal logic inputs with pull-high resistors. Wake-up After the system enters the Power Down Mode, it can be woken up from one of various sources listed as follows:
* An external reset * An external falling edge on any of the I/O pins * A system interrupt * A WDT overflow
No matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 1024 system clock periods will be required before normal system operation resumes. However, if the wake-up has originated due to an interrupt, the actual interrupt subroutine execution will be delayed by an additional one or more cycles. If the wake-up results in the execution of the next instruction following the HALT instruction, this will be executed immediately after the 1024 system clock period delay has ended.
Low Voltage Detector - LVD
This Low Voltage Detect internal function provides a means for the user to monitor when the power supply voltage falls below a certain fixed level as specified in the DC characteristics. The LVD is enabled using a configuration option. Bit 3 of the MODE register is used to monitor the overall function of the LVD. Under normal operation, and when the power supply voltage is above the specified VLVD value in the DC characteristic section, the 2.2LVD bit will remain at a zero value. If the power supply voltage should fall below this VLVD value then the 2.2LVD bit will change to a high value indicating a low voltage condition. Note that the LVDO bit is a read-only bit. By polling the 2.2LVD bit in the MODE register, the application program can therefore determine the presence of a low voltage condition. It is important not to confuse the LVD with the LVR function. In the LVR function an automatic reset will be generated by the microcontroller, whereas in the LVD function only the 2.2LVD bit will be affected with no influence on other microcontroller functions.
If the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the HALT instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pins on Port A or any nibble on the other ports can be setup via an individual configuration option to permit a negative transition on the pin to wake-up the system. When a Port pins wake-up occurs, the program will resume execution at the instruction following the HALT instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the HALT instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the Power Down Mode, the wake-up function of the related interrupt will be disabled.
Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. It operates by providing a device reset when the WDT counter overflows. The WDT clock is supplied by one of two sources selected by configuration option: its own self-contained dedicated internal WDT oscillator, or the instruction clock which is the system clock divided by 4. Note that if the WDT configuration option has been disabled, then any instruction relating to its operation will result in no operation. The internal WDT oscillator has an approximate period of 32ms at a supply voltage of 5V. If selected, it is first divided by 256 via an 8-stage counter to give a nominal period of 8ms. Note that this period can vary with VDD, temperature and process variations. For longer WDT time-out periods the WDT prescaler can be utilized. By writing the required value to bits 0, 1 and 2 of the WDTS register, known as WS0, WS1 and WS2, longer time-out periods can be achieved. With WS0, WS1 and WS2 all
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b7 W S2 W S1 b0 W S0 W D T S R e g is te r W D T p r e s c a le r r a te s e le c t W DTR W S0 W S1 W S2 1 :1 0 0 0 1 :2 1 0 0 1 :4 0 1 0 1 :8 1 1 0 1 :1 0 0 1 1 :3 1 0 1 1 :6 0 1 1 1 :1 1 1 1 2 4 N otused a te
6 28
Watchdog Timer Register
C L R W D T 1 F la g C L R W D T 2 F la g 1 o r 2 In s tr u c tio n s fS
YS
C le a r W D T T y p e C o n fig u r a tio n O p tio n CLR W D T C lo c k S o u r c e C o n fig u r a tio n O p tio n 8 - b it C o u n te r ( 2 5 6 )
/4
CLR 7 - b it P r e s c a le r
W D T O s c illa to r W D T C lo c k S o u r c e
8 -to -1 M U X W D T T im e - o u t
W S0~W S2
Watchdog Timer equal to 1, the division ratio is 1:128 which gives a maximum time-out period of about 1.0s. A configuration option can select the instruction clock, which is the system clock divided by 4, as the WDT clock source instead of the internal WDT oscillator. If the instruction clock is used as the clock source, it must be noted that when the system enters the Power Down Mode, as the system clock is stopped, then the WDT clock source will also be stopped. Therefore the WDT will lose its protecting purposes. In such cases the system cannot be restarted by the WDT and can only be restarted using external signals. For systems that operate in noisy environments, using the internal WDT oscillator is therefore the recommended choice. Under normal program operation, a WDT time-out will initialise a device reset and set the status bit TO. However, if the system is in the Power Down Mode, when a WDT time-out occurs, only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the WDT and the WDT prescaler. The first is an external hardware reset, which means a low level on the RES pin, the second is using the watchdog software instructions and the third is via a HALT instruction. There are two methods of using software instructions to clear the Watchdog Timer, one of which must be chosen by configuration option. The first option is to use the single CLR WDT instruction while the second is to use the two commands CLR WDT1 and CLR WDT2. For the first option, a simple execution of CLR WDT will clear the WDT while for the second option, both CLR WDT1 and CLR WDT2 must both be executed to successfully clear the WDT. Note that for this second option, if CLR WDT1 is used to clear the WDT, successive executions of this instruction will have no effect, only the execution of a CLR WDT2 instruction will clear the WDT. Similarly, after the CLR WDT2 instruction has been executed, only a successive CLR WDT1 instruction can clear the Watchdog Timer.
Pulse Width Modulator
The device is provided with two Pulse Width Modulator, PWM, outputs. The internal PWM function within the device is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the PWM output pins, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled the choice of generated waveform is extremely flexible. PWM Registers There are a total of five registers to control the PWM function. Each PWM output has a pair of registers, one to control the waveform period, and another to control the duty cycle. The period control registers are known as PWMBR0 and PWMBR1 while the duty cycle registers have the name PWM0DR and PWM1DR. An addition register, the PWMCTL register, is the control register for both outputs and contains the output enable/disable bits and also select the PWM clock source to be either fSYS or fSYS/4. 58 October 30, 2009
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b7 U S B d is P W M 1 _ e n P W M 0 _ e n P W M 1 _ S b0 PW M 0_S P W M C T L R e g is te r P W M 0 c lo c k s o u r c e 1 : fS Y S /4 ( d e fa u lt) 0 : fS Y S P W M 1 c lo c k s o u r c e 1 : fS Y S /4 ( d e fa u lt) 0 : fS Y S P W M e n a b le /d is a b le 1 : e n a b le 0 : d is a b le ( d e fa u lt) D e s c r ib e d e ls e w h e r e 1 : U S B S IE d is a b le ( d e fa u lt) 0 : U S B S IE e n a b le N o t im p le m e n te d , r e a d a s " 0 "
Pulse Width Modulator Control Register
PW M
H ig h P u ls e
need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Overview The device contains a multi-channel channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into an 12-bit digital value. The number of available channels depends upon which package type is chosen. Package Channels Resolution Input Pins PB4~PB7 PC5~PC7 PB0~PB7 PB0~PB7 PC0~PC7
PW M
C y c le P e r io d
PWM Operation The clock source for the PWM output is selected to be either fSYS or fSYS/4 using bits in the PWMCTL register. The period of the PWM waveform for each PWM output is setup by programming the required value into the PWMBR0 or PWMBR1 register using the following formula: PWM waveform period = 256(1/fSYS)(PWMBRn+1), or 256 (4/fSYS) (PWMBRn+1) depending upon which clock source is selected. For example if the system frequency is 6MHz, if fSYS/4 is selected as the PWM source clock and a decimal value of 17 is in the PWMBRn register, then the PWM waveform will have a period of {256(4/(610-6)18}= 3072ms which is equivalent to a frequency of 0.325kHz. The duty cycle for each PWM output can be by configured using the PWM0DR and PWM1DR registers. The value in these registers represents the ratio of the high to low pulse in each waveform period. Therefore the ratio of the high pulse to the low pulse, which is in fact just the duty cycle, is given by (PWMnDR+1)/256. The PWM output can now be controlled using the enable/disable bits in the CTRL register. As the PWM outputs are pin shared with normal I/O pins they must first be setup as outputs for correct operation. When the PWM output is disabled using the enable/disable bit in the CTRL register it can still be used as a normal I/O pin.
28-pin 32-pin 44-pin
7 8 16
12-bit 12-bit 12-bit
The A/D block diagram shows the overall internal structure of the A/D converter, together with its associated registers. A/D Converter Data Registers - ADRL, ADRH The devices, which contain a single12-bit A/D converter, require two data registers, known as ADRL and ADRH . After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. In the following tables, D0~D7 are the A/D conversion data result bits. Register ADRL ADRH Bit 7 D3 Bit 6 D2 Bit 5 D1 Bit 4 D0 D8 Bit 3 3/4 D7 Bit 2 3/4 D6 Bit 1 3/4 D5 Bit 0 3/4 D4
Analog to Digital Converter
The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the Rev. 1.10 59
D11 D10 D9
Note: D11~D0 is the A/D conversion result data bit MSB~LSB. A/D Data Register
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ADC
YS YS
fS fS
S o u rc e /3 , fS Y S /6 , /8 , fS Y S /1 6
C lo c k D iv id e R a tio N V
REF
ACSR
R e g is te r
A /D
r e fe r e n c e v o lta g e A /D D a ta R e g is te r s
P B 0 /A N 0 ~ P B 7 /A N 7 P C 0 /A N 8 ~ P C 7 /A N 1 5
ADC
ADR
PC R0~PC R3 P in C o n fig u r a tio n B its
AD CS0~ADCS3 C h a n n e l S e le c t B its
START
EOCB
ADCR R e g is te r
S ta r t B it E n d o f C o n v e r s io n B it
A/D Converter Structure
b7 START EO CB b0 ACS0
ACS3
ACS2
ACS1
ADCR
R e g is te r channel CS2 ACS1 0 0 0 0 0 1 0 1 : : : : 1 1 ACS0 0 1 0 1 : : 1
S e le c t A /D A ACS3 0 0 0 0 : : 1
:AN :AN :AN :AN : : :AN 1 2 3
0
15
N o t im p le m e n te d , r e a d a s " 0 " E n d o f A /D c o n v e r s io n fla g 1 : n o t e n d o f A /D c o n v e r s io n - A /D c o n v e r s io n w a itin g o r in p r o g r e s s 0 : e n d o f A /D c o n v e r s io n - A /D c o n v e r s io n e n d e d S ta r t th e A /D c o n v e r s io n 0 (R) 1 (R) 0 : S ta rt 0 (R) 1 : R e s e t A /D c o n v e rte r a n d s e t E O C B to "1 "
A/D Converter Control Register
A/D Converter Control Register - ADCR To control the function and operation of the A/D converter, control registers known as ADCR and ADSR are provided. These 8-bit registers define functions such as the selection of which analog channel is connected to the internal A/D converter, which pins are used as analog inputs and which are used as normal I/Os as well as controlling the start function and monitoring the A/D converter end of conversion status. One section of this register contains the bits ACS3~ACS0 which define the channel number. As each of the devices contains only one actual analog to digital converter circuit, each of the individual analog inputs must be routed to the converter. It is the function of the ACS3~ACS0 bits in the ADCR register to determine which analog channel is actually connected to the internal A/D converter. The START bit in the ADCR register is used to start and reset the A/D converter. When the microcontroller sets this bit from low to high and then low again, an analog to
digital conversion cycle will be initiated. When the START bit is brought from low to high but not low again, the EOCB bit in the ADCR register will be set to a 1 and the analog to digital converter will be reset. It is the START bit that is used to control the overall on/off operation of the internal analog to digital converter. The EOCB bit in the ADCR register is used to indicate when the analog to digital conversion process is complete. This bit will be automatically set to 0 by the microcontroller after a conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. This A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can be used to poll the EOCB bit in the ADCR register to check whether it has been cleared as an alternative method of detecting the end of an A/D conversion cycle.
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b7 TEST
PCR3 PCR2 PCR1 PCR0 ADON
b0 ADCS1ADCS0
ACSR
R e g is te r c lo c k s o u r c e sys sys sys sys te m te m te m te m c lo c lo c lo c lo c k /3 c k /6 c k /8 c k /1 6
S e le c t A /D c o n v e r te r ADCS0 ADCS1 : 0 0 : 1 0 : 0 1 : 1 1 0 : d is a b le ( d e fa u lt) 1 : e n a b le P B a n d P C A /D PCR2 PCR3 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1
channelcon P PCR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
fig u r a tio n CR0 0 :P 1 :P 0 :P :P 1 0 :P :P 1 0 :P 1 :P 0 :P 1 :P 0 :P 1 :P 0 :P 1 :P 0 :P 1 :P
B an B0a B0~ B0~ B0~ B0~ B0~ B0~ B0~ B0~ B0~ B0~ B0~ B0~ B0~ B0~
dP sA PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB7 PB7 PB7 PB7 PB7 PB7 PB7
CA N0 as as as as as as as ,P ,P ,P ,P ,P ,P ,P C
/D
c h a n n e l - a ll o ff AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN0 1a 2a 3a 4a 5a 7a
C C C C C C
AN0~ AN0~ AN0~ AN0~ AN0~ AN0~ AN0~ 0 as 0~PC 0~PC 0~PC 0~PC 0~PC 0~PC
~AN sAN sAN sAN sAN sAN sAN
0~A 0~A 0~A 0~A 0~A 0~A
8
N9 N1 N1 N1 N1 N1 0
1 2 5 3
F o r te s t m o d e u s e o n ly
A/D Converter Clock Source Register A/D Converter Clock Source Register - ACSR The clock source for the A/D converter, which originates from the system clock fSYS, is first divided by a division ratio, the value of which is determined by the ADCS1 and ADCS0 bits in the ACSR register. The ACSR control register also contains the PCR3~PCR0 bits which determine which pins on Port B and Port C are used as analog inputs for the A/D converter and which pins are to be used as normal I/O pins. If the 4-bit address on PCR3~PCR0 has a value of 1111 or higher, then all 16 pins, namely AN0~ AN15 will all be set as analog inputs. Note that if the PCR3~PCR0 bits are all set to zero, then all the Port B and Port C pins will be setup as normal I/Os and the internal A/D converter circuitry will be powered off to reduce the power consumption. Although the A/D clock source is determined by the system clock fSYS, and by bits ADCS1 and ADCS0, there are some limitations on the maximum A/D clock source speed that can be selected. As the minimum value of permissible A/D clock period, tAD, is 0.5ms, care must be taken for system clock speeds in excess of 4MHz. For system clock speeds in excess of 4MHz, the ADCS1 and ADCS0 bits should not be set to 00. Doing so will give A/D clock periods that are less than the minimum A/D clock period which may result in inaccurate A/D conversion values. Refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specified minimum A/D Clock Period. A/D Input Pins All of the A/D analog input pins are pin-shared with the I/O pins on Port B and Port C. Bits PCR3~PCR0 in the ACSR register, not configuration options, determine whether the input pins are setup as normal Port B and Port C input/output pins or whether they are setup as analog inputs. In this way, pins can be changed under program control to change their function from normal I/O operation to analog inputs and vice versa. Pull-high resistors, which are setup through configuration options, apply to the input pins only when they are used as normal I/O pins, if setup as A/D inputs the pull-high resistors will be automatically disconnected. Note that it is not necessary to first setup the A/D pin as an input in the PBC or PCC port control register to enable the A/D input as when the PCR3~PCR0 bits enable an A/D input, the status of the port control register will be overridden. Initialising the A/D Converter The internal A/D converter must be initialised in a special way. Each time the Port B and Port C A/D channel selection bits are modified by the program, the A/D converter must be re-initialised. If the A/D converter is not initialised after the channel selection bits are changed, the EOCB flag may have an undefined value, which may produce a false end of conversion signal. To initialise the A/D converter after the channel selection bits have changed, then, within a time frame of one to ten instruction cycles, the START bit in the ADCR register must first be set high and then immediately cleared to zero. This will ensure that the EOCB flag is correctly set to a high condition. 61 October 30, 2009
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S T A R T b it s e t h ig h w ith in o n e to te n in s tr u c tio n c y c le s a fte r th e P C R 0 ~ P C R 2 b its c h a n g e s ta te START
EOCB PC R3~ PCR0
A /D
s a m p lin g tim e
D
A /D s a m p lin g tim e 3 2 tA
D
A /D s a m p lin g tim e 3 2 tA
D
3 2 tA 000B
011B
100B
000B 1 . P o rt B a n d P o rt C s e tu p a s I/O s 2 . A /D c o n v e r te r is p o w e r e d o ff to r e d u c e p o w e r c o n s u m p tio n
AC S3~ ACS0
000B P o w e r-o n R eset R e s e t A /D c o n v e rte r 1 : D e fin e P B , P C c o n fig u r a tio n 2 : S e le c t a n a lo g c h a n n e l
010B S ta rt o f A /D c o n v e r s io n
000B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n
001B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n
D o n 't c a r e
E n d o f A /D c o n v e r s io n tA
DC
tA A /D N o te : A /D c lo c k m u s t b e fS
YS
DC
tA /8 , fS /1 6
DC
c o n v e r s io n tim e
YS
A /D c o n v e r s io n tim e
A /D c o n v e r s io n tim e
/3 , fS
/6 , fS
YS
YS
A/D Conversion Timing Summary of A/D Conversion Steps The following summarises the individual steps that should be executed in order to implement an A/D conversion process.
* Step 1
Note:
When checking for the end of the conversion process, if the method of polling the EOCB bit in the ADCR register is used, the interrupt enable step above can be omitted.
Select the required A/D conversion clock by correctly programming bits ADCS1 and ADCS0 in the ACSR register.
* Step 2
The A/D conversion timing diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. The setting up and operation of the A/D converter function is fully under the control of the application program as there are no configuration options associated with the A/D converter. After an A/D conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. The time taken for the A/D conversion is 76tAD where tAD is equal to the A/D clock period. Programming Considerations When programming, special attention must be given to the A/D channel selection bits in the ADSR register. If these bits are all cleared to zero no external pins will be selected for use as A/D input pins allowing the pins to be used as normal I/O pins. When this happens the power supplied to the internal A/D circuitry will be reduced resulting in a reduction of supply current. This ability to reduce power by turning off the internal A/D function by clearing the A/D channel selection bits may be an important consideration in battery powered applications. Another important programming consideration is that when the A/D channel selection bits change value, the A/D converter must be re-initialised. This is achieved by pulsing the START bit in the ADCR register immediately after the channel selection bits have changed state. The exception to this is where the channel selection bits are all cleared, in which case the A/D converter is not required to be re-initialised.
Select which channel is to be connected to the internal A/D converter by correctly programming the ACS3~ ACS0 bits which are also contained in the ADCR register.
* Step 3
Select which pins on Port B and Port C are to be used as A/D inputs and configure them as A/D input pins by correctly programming the PCR3~PCR0 bits in the ACSR register.
* Step 4
If the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the A/D converter interrupt function is active. The master interrupt control bit, EMI, in the INTC interrupt control register must be set to 1 and the A/D converter interrupt bit, EADI, in the INTC register must also be set to 1.
* Step 5
The analog to digital conversion process can now be initialised by setting the START bit in the ADCR register from 0 to 1 and then to 0 again. Note that this bit should have been originally set to 0.
* Step 6
To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR register can be polled. The conversion process is complete when this bit goes low. When this occurs the A/D data registers ADR can be read to obtain the conversion value. As an alternative method if the interrupts are enabled and the stack is not full, the program can wait for an A/D interrupt to occur. Rev. 1.10 62
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A/D Programming Example The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using an EOCB polling method to detect the end of conversion clr EADI ; disable ADC interrupt mov a,00011001 mov acsr,a ; setup the ACSR register to select fsys/6 as the A/D clock ; setup the ACSR register to configure Port PB0~PB2 as A/D ; Inputs mov a,00000000 mov adcr,a ; setup the ADCR register and select AN0 to be connected to ; the A/D converter ; As the Port B and Port C channel bits have changed the ; following START signal (0(R)1(R)0) must be issued within ; 10 instruction cycles : Start_conversion: clr START set START ; reset A/D clr START ; start A/D Polling_: sz EOCB ; poll the ADCR register EOCB bit to detect end ; of A/D conversion jmp polling_EOC ; continue polling mov a,ADR ; read conversion result value mov adrl_buffer,a ; save result to user defined register : jmp start_conversion ; start next A/D conversion Example: using the interrupt method to detect the end of conversion clr EADI ; disable ADC interrupt mov a,00011001B mov ACSR,a ; setup the ACSR register to select fSYS/6 as the A/D clock mov mov a,00000000B ADCR,a : ; setup ADCR register to configure Port PB0~PB2 ; as A/D inputs ; and select AN0 to be connected to the A/D ; As the Port B channel bits have changed the ; following START signal(0(R)1(R)0) must be issued ; within 10 instruction cycles : Start_conversion: clr START set START clr START clr ADF set EADI set EMI : : : ; ADC interrupt service routine ADC_: mov acc_stack,a a,STATUS mov status_stack,a : : mov a,ADR mov adrl_buffer,a : : EXIT_INT_ISR: mov a,status_stack mov STATUS,a mov a,acc_stack
; ; ; ; ;
reset A/D start A/D clear ADC interrupt request flag enable ADC interrupt enable global interrupt
; save ACC to user defined memory ; save STATUS to user defined memory ; read conversion result value ; save result to user defined register
; restore STATUS from user defined memory ; restore ACC from user defined memory
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1 .5 L S B FFFH FFEH FFDH A /D C o n v e r s io n R e s u lt 03H 02H 01H 0 1 2 4093 4094 A n a lo g In p u t V o lta g e 3 4095 4096 ( V DD ) 4096 0 .5 L S B
Ideal A/D Transfer Function
A/D Transfer Function As the device contain a 12-bit A/D converter, its full-scale converted digitised value is equal to FFFH. Since the full-scale analog input value is equal to the VDD voltage, this gives a single bit analog input value of VDD/4096. The diagram show the ideal transfer function between the analog input value and the digitised output value for the A/D converter. Note that to reduce the quantisation error, a 2.5 LSB offset is added to the A/D Converter input. Except for the digitised zero value, the subsequent digitised values will change at a point 2.5 LSB below where they would change without the offset, and the last full scale digitised value will change at a point 2.5 LSB below the VDD level.
SPI Registers There are two registers for control of the SPI Interface. These are the SBCRA/B register which is the control register and the SBDRA/B which is the data register. The SBCRA/B register is used to setup the required setup parameters for the SPI bus and also used to store associated operating flags, while the SBDRA/B register is used for data storage. After Power on, the contents of the SBDRA/B register will be in an unknown condition while the SBCRA/B register will default to the condition below:
CKSn M1n M0n SBENn MLSn CSENn WCOLn TRFn 0 1 1 0 0 0 0 0
SPI Serial Interface
The device includes two SPI Serial Interfaces. The SPI interface is a full duplex serial data link, originally designed by Motorola, which allows multiple devices connected to the same SPI bus to communicate with each other. The devices communicate using a master/slave technique where only the single master device can initiate a data transfer. A simple four line signal bus is used for all communication. SPI Interface Communication Four lines are used for each SPI function. These are, SDIA/B - Serial Data Input, SDOA/B - Serial Data Output, SCLKA/B - Serial Clock and SCSA/B - Slave Select. Note that the condition of the Slave Select line is conditioned by the CSENA/B bit in the SBCRA/B control register. If the CSENA/B bit is high then the SCSA/B line is active while if the bit is low then the SCSA/B line will be in a floating condition. The accompanying timing diagram depicts the basic timing protocol of the SPI bus.
Note: n where n=A~B Note that data written to the SBDRA/B register will only be written to the TXRX buffer, whereas data read from the SBDRA/B register will actual be read from the register. SPI Bus Enable/Disable To enable the SPI bus, the SBENA/B bit should be set high, then the SCLKA/B, SDIA/B, SDOA/B and SCSA/B lines should all be zero, then wait for data to be written to the SBDRA/B (TXRX buffer) register. For the Master Mode, after data has been written to the SBDRA/B (TXRX buffer) register then transmission or reception will start automatically. When all the data has been transferred, the TRFA/B bit should be set. For the Slave Mode, when clock pulses are received on SCLKA/B, data in the TXRX buffer will be shifted out or data on SDIA/B will be shifted in. To Disable the SPI bus SCLKA/B, SDIA/B, SDOA/B, SCSA/B should be floating.
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October 30, 2009
HT82A623R/HT82A6208/HT82A6216
SPI Operation All communication is carried out using the 4-line interface for both Master or Slave Mode. The timing diagram shows the basic operation of the bus. The CSENA/B bit in the SBCRA/B register controls the overall function of the SPI interface. Setting this bit high, will enable the SPI interface by allowing the SCSA/B line to be active, which can then be used to control the SPI interface. If the CSENA/B bit is low, the SPI interface will be disabled and the SCSA/B line will be in a floating condition and can therefore not be used for control of the SPI interface. The SBENA/B bit in the SBCRA/B register must also be high which will place the SDIA/B line in a floating condition and the SDOA/B line high. If in the Master Mode the SCLKA/B line will be either high or low depending upon the clock polarity configuration option. If in the Slave Mode the SCLKA/B line will be in a floating condition. If SBENA/B is low then the bus will be disabled and SCSA/B, SDIA/B, SDOA/B and SCLKA/B will all be in a floating condition. In the Master Mode, the Master will always generate the clock signal. The clock and data transmission will be initiated after data has been written to the SBDRA/B register. In the Slave Mode, the clock signal will be received from an external master device for both data transmission or reception. The following sequences show the order to be followed for data transfer in both Master and Slave Mode:
* Master Mode
Step 1. Select the clock source using the CKSA/B bit in the SBCRA/B control register Step 2. Setup the M0A/B and M1A/B bits in the SBCRA/B control register to select the Master Mode and the required Baud rate. Values of 00, 01 or 10 can be selected. Step 3. Setup the CSENA/B bit and setup the MLSA/B bit to choose if the data is MSB or LSB first, this must be same as the Slave device. Step 4. Setup the SBENA/B bit in the SBCRA/B control register to enable the SPI interface.
D a ta B u s SBDR ( R e c e iv e d D a ta R e g is te r )
D7D6D5D4D3D2D1D0 M
U X
SDO
B u ffe r S B E N A /B
S D O A /B
M LS M U X M U X C0C1C2 In te r n a l B a u d R a te C lo c k S C K A /B EN a n d , s ta rt C lo c k P o la r ity a n d , s ta rt
S D IA /B
T R F A /B AND W C O L A /B F la g
M a s te r o r S la v e S B E N A /B In te r n a l B u s y F la g S B E N A /B
W r ite S B D R A /B
a n d , s ta rt EN
W r ite S B D R A /B E n a b le /D is a b le W r ite S B D R A /B
S C S A /B
M a s te r o r S la v e S B E N A /B C S E N A /B
SPI Block Diagram Note: WCOLA/B: set by SPI cleared by users CSENA/B: enable/disable chip selection function pin master mode: 1/0 = with/without SCSA/B output function Slave mode: 1/0 = with/without SCSA/B input control function SBENA/B: enable/disable serial bus (0: initialise all status flags) when SBENA/B=0, all status flags should be initialised when SBENA/B=1, all SPI related function pins should stay at floating state TRFA/B: 1 = data transmitted or received, 0= data is transmitting or still not received CPOL: I/O = clock polarity rising/falling edge : mask option If clock polarity set to rising edge (SPIA_CPOL/SPIB_CPOL=1), serial clock timing follow CLK, otherwise (SPIA_CPOL/SPIB_CPOL=0) CLK is the serial clock timing. 65 October 30, 2009
Rev. 1.10
HT82A623R/HT82A6208/HT82A6216
Step 5. For write operations: write the data to the SBDRA/B register, which will actually place the data into the TXRX buffer. Then use the SCLKA/B and SCSA/B lines to output the data. Goto to step 6.For read operations: the data transferred in on the SDIA/B line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SBDRA/B register. Step 6. Check the WCOLA/B bit, if set high then a collision error has occurred so return to step5. If equal to zero then go to the following step. Step 7. Check the TRFA/B bit or wait for an SPI serial bus interrupt. Step 8. Read data from the SBDRA/B register. Step 9. Clear TRFA/B. Step10. Goto step 5.
* Slave Mode:
For read operations: the data transferred in on the SDIA/B line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SBDRA/B register. Step 6. Check the WCOLA/B bit, if set high then a collision error has occurred so return to step5. If equal to zero then goto the following step. Step 7. Check the TRFA/B bit or wait for an SPI serial bus interrupt. Step 8. Read data from the SBDRA/B register. Step 9. Clear TRFA/B Step10. step 5 SPI Configuration Options and Status Control One option is to enable the operation of the WCOLA/B, write collision bit, in the SBCRA/B register. Some control in SPIR register. The SPIA_CPOL/ SPIB_CPOL select the clock polarity of the SCK line. The SPIA_MODE/ SPIB_MODE select SPI data output mode. SPI include four pins , can share I/O mode status . The status control combine with four bits for SPI and SBCRA/B register. Include SPIA_CSEN/SPIB_CSEN, SPIA_IO/SPIB_IO for SPI register and CSENA/B, SBENA/B for SBCRA/B register.
Step 1. The CKSA/B bit has a dont care value in the slave mode. Step 2. Setup the M0A/B and M1A/B bits to 00 to select the Slave Mode. The CKSA/B bit is dont care. Step 3. Setup the CSENA/B bit and setup the MLSA/B bit to choose if the data is MSB or LSB first, this must be same as the Master device. Step 4. Setup the SBENA/B bit in the SBCRA/B control register to enable the SPI interface. Step 5. For write operations: write data to the SBCRA/B register, which will actually place the data into the TXRX register, then wait for the master clock and SCSA/B signal. After this goto step 6.
Control Bit for Register SPIn_IO 0 1 1 1 1 1 Note: SPIn_CSEN x 0 0 1 1 1 n where n=A~B X: dont care (Z) floating SBENn x 0 1 0 1 1 CSENn x x x x 0 1 SCSn I/O Mode I/O Mode I/O Mode I/O Mode
SPI Share Function Pins Status SCKn I/O Mode I/O Mode SPI Mode I/O Mode SPI Mode SPI Mode SDOn I/O Mode I/O Mode SPI Mode I/O Mode SPI Mode SPI Mode SDIn I/O Mode I/O Mode SPI Mode(Z) I/O Mode SPI Mode(Z) SPI Mode(Z)
SPI Mode (Z) SPI Mode
Rev. 1.10
66
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
S P I_ m o d e = 0 P A 0 /S C S A , P B 0 /S C S B (S P IA _ C S E N /S P IB _ C S E N = 1 ) P A 1 /S C L K A , P B 1 /S C L K B (S P IA _ C P O L /S P IB _ C P O L = 1 ) P A 1 /S C L K A , P B 1 /S C L K B (S P IA _ C P O L /S P IB _ C P O L = 0 ) P A 2 /S D IA , P B 2 /S D IB D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7
S B E N A /B = 1 , C S E N A /B = 0 a n d w r ite d a ta to S B D R A /B ( if p u ll- h ig h e d ) S B E N A /B = C S E N A /B = 1 a n d w r ite d a ta to S B D R A /B
P A 3 /S D O A , P B 3 /S D O B
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
S P I_ m o d e = 1 P A 0 /S C S A , P B 0 /S C S B (S P IA _ C S E N /S P IB _ C S E N = 1 ) P A 1 /S C L K A , P B 1 /S C L K B (S P IA _ C P O L /S P IB _ C P O L = 1 ) P A 1 /S C L K A , P B 1 /S C L K B (S P IA _ C P O L /S P IB _ C P O L = 0 ) P A 2 /S D IA , P B 2 /S D IB D 7 /D 0 D 6 /D 1
S B E N A /B = 1 , C S E N A /B = 0 a n d w r ite d a ta to S B D R A /B ( if p u ll- h ig h e d ) S B E N A /B = C S E N A /B = 1 a n d w r ite d a ta to S B D R A /B
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
P A 3 /S D O A , P B 3 /S D O B
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
D7 SBCRn D e fa u lt 0 D7 U SBDRn D e fa u lt CKSn
D6 M 1n 1 D6 U
D5 M 0n 1 D5 U
D4 SBENn 0 D4 U
D3 M LSn 0 D3 U
D2 CSENn 0 D2 U
D1 W C O Ln 0 D1 U
D0 TRFn 0 D0 U S B C R n : S e r ia l B u s C o n tr o l R e g is te r S B D R n : S s e r ia l B u s D A T A R e g is te r
N o te : "n " w h e re n = A ~ B "U " m e a n s u n c h a n g e d .
SPI Bus Timing
Rev. 1.10
67
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
Error Detection The WCOLA/B bit in the SBCRA/B register is provided to indicate errors during data transfer. The bit is set by the Serial Interface but must be cleared by the application program. This bit indicates a data collision has occurred which happens if a write to the SBDRA/B register takes place during a data transfer operation and will prevent the write operation from continuing. The bit will be set high by the Serial Interface but has to be cleared by the user application program. The overall function of the WCOLA/B bit can be disabled or enabled by a configuration option.
b7 CKS M1 M0 SBEN M LS
b0 CSENW COL TRF S B C R A /S B C R B R e g is te r T r a n s m itt/R e c e iv e fla g 0 : N o t c o m p le te 1 : T r a n s m is s io n /r e c e p tio n c o m p le te W r ite c o llis io n b it 0 : C o llis io n fr e e 1 : C o llis io n d e te c te d S e le c tio n s ig n a l e n a b le /d is a b le b it 0 : S C S A /S C S B flo a tin g 1 : E n a b le M S B /L S B fir s t b it 0 : L S B s h ift fir s t 1 : M S B s h ift fir s t S e r ia l B 0 : D is a b 1:Enab Depe u s e n a b le /d is a b le b it le le n d e n t u p o n C S E N A /C S E N B b it v e /B a u d r a te b its M as M as M as S la v te r, te r, te r, em b a u d ra te : fS b a u d ra te : fS b a u d ra te : fS ode
IO IO IO
M a s te r /S la M1 M0 0 0 0 1 1 0 1 1
/4
/1 6
C lo c k s o u r c e s e le c t b it 0 : f S IO = f S Y S / 4 1 : f S IO = f S Y S
SPI Interface Control Register
Rev. 1.10
68
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
Programming Considerations When the device is placed into the Power Down Mode note that data reception and transmission will continue. The TRFA/B bit is used to generate an interrupt when the data has been transferred or received. SPI Transfer Control Flowchart
A
S P I T ra n s fe r C le a r W C O L A /B
W r ite D a ta in to S B D R A /B
M a s te r
M a s te r o r S la v e
S la v e Yes W C O L A /B = 1 ?
S IM [2 :0 ]= 0 0 0 , 0 0 1 ,0 1 0 ,0 1 1 o r 1 0 0
S IM [2 :0 ]= 1 0 1
No
No C o n fig u r e C S E N A /B a n d M L S S P IA _ IO = 1 o r S P IB _ IO = 1
T r a n s m is s io n C o m p le te d ? (T R F A /B = 1 ? )
Yes re a d d a ta fro m S B D R A /B
A c le a r T R F A /B
T ra n s fe r F in is h e d ? Yes END
No
Rev. 1.10
69
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
Bit No. 0 Label SPIA_IO 1: IO, 0: SPI (default) 1: SPI first output the data immediately after the SPI is enable. And SPI output the data in the falling edge (polarity=1) or rising edge (polarity=0); SPI read data in the in the rising edge (polarity=1) or falling edge (polarity=0) 0: SPI output the data in the rising edge (polarity=1) or falling edge (polarity=0); SPI read data in the in the falling edge (polarity=1) or rising edge (polarity=0); (default) 1: clock polarity rising 0: clock polarity falling (default falling) 1: SPI_CSEN: Enable , this bit is used to enable/disable software CSEN function (default enable) 0: SPI_CSEN disable, SCSA define as GPIO 1: IO, 0: SPI (default) 1: SPI first output the data immediately after the SPI is enable. And SPI output the data in the falling edge (polarity=1) or rising edge (polarity=0); SPI read data in the in the rising edge (polarity=1) or falling edge (polarity=0) 0: SPI output the data in the rising edge (polarity=1) or falling edge (polarity=0); SPI read data in the in the falling edge (polarity=1) or rising edge (polarity=0); (default) 1: clock polarity rising 0: clock polarity falling (default falling) 1: SPI_CSEN: Enable, this bit is used to enable/disable software CSEN function (default enable) 0: SPI_CSEN disable, SCSB define as GPIO SPI Register Function
1
SPIA_MODE
2
SPIA_CPOL
3 4
SPIA_CSEN SPIB_IO
5
SPIB_MODE
6
SPIB_CPOL
7
SPIB_CSEN
USB Interface
The device includes a USB interface function allowing for the convenient design of USB peripheral products. The USB disable/enable control bit USBdis is in the PWMCTL Register. If the USB is disabled, then V33O and the D+/D- lines will be floating and the USB SIE will be disabled. Power Plane There are four power planes for the device: USB SIE VDD, VDDIO and the MCU VDD and Flash memory power for the HT82A6208/HT82A6216. For the USB SIE VDD will supply all circuits related to the USB SIE and be sourced from pin UBUS. Once the USB is removed from the USB and there is no power in the USB BUS, the USB SIE circuit is no longer operational. For the PB port, it can be configured using a configuration option to define the if the pins PB0~PB7 are supplied by either the MCU VDD, or if pins PB0~PB6 are supplied by the power pin VDDIO, in which case power will be supplied on pin PB7. In the latter configuration, PB7 will be configured as a power pin VDDIO and not a normal I/O pin. For the MCU VDD, it supplies all the HT82A623R circuit except the USB SIE which is supply by UBUS. For the HT82A6208 and HT82A6216 the internal Flash memory is supplied by VCC. Rev. 1.10 70 USB Suspend Wake-Up Remote Wake-Up If there is no signal on the USB bus for over 3ms, the device will enter a suspend mode. The Suspend flag, SUSP, in the USC register, will then be set high and a USB interrupt will be generated to indicate that the device should jump to the suspend state to meet the requirements of the USB suspend current spec. In order to meet the requirements of the suspend current, the firmware should disable the USB clock by clearing the USBCKEN bit to zero. The suspend current can be further decreased by setting the SUSP2 bit in the UCC register. When the resume signal is sent out by the host, the device will be woken up the by the USB interrupt and the Resume bit in the USC register will be set. To ensure correct device operation, the program must set the USBCKEN bit in the UCC register high and clear the SUSP2 bit in the UCC register. The Resume signal will be cleared before the Idle signal is sent out by the host and the Suspend line in the USC register will change to zero. So when the MCU
SUSPEND U S B R e s u m e S ig n a l
U S B _ IN T
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
detects the Suspend bit in the USC register, the condition of the Resume line should be noted and taken into consideration. The device has a remote wake up function which can wake-up the USB Host by sending a wake-up pulse through RMWK in the USC register. Once the USB Host receives a wake-up signal from the device it will send a Resume signal to the device.
SUSPEND M in . 1 USB CLK RMW K U S B R e s u m e S ig n a l M in . 2 .5 m s
USB Interface Operation The device has 8 Endpoints, EP0~EP3. EP0 supports Control transfer. All EP1~EP3 support Interrupt or Bulk transfer. All endpoints except EP0 can be configured as 8, 16, 32 or 64 FIFO size using the register UFC0 and UFC1. EP0 has an 8-byte FIFO size. The Total FIFO size is 64+8 bytes. The URD in the USC register is the USB reset signal control function definition bit.
U S B _ IN T
Bit No. 0 1 2 3 4 5 6 7
Label ESD PUB SE0 SE1 PS2/DAI PS2/CKI PS2/DAO PS2/CKO
Function This bit will set to 1 when there are ESD issue. This bit is set by SIE and clear by F/W. Bit3=1, D+, and D- have a 500kW pull-high Bit3=0, no pull-high (default on MCU reset) This bit is used to indicate the SIE has detect a SE0 noise in the USB bus. This bit is set by SIE and clear by F/W. This bit is used to indicate the SIE has detect a SE1 noise in the USB bus. This bit is set by SIE and clear by F/W. USBD-/DATA input. USBD+/CLK input. Output for driving USBD-/DATA pin, when work under 3D PS2 mouse function. Default value is 1. Output for driving USBD+/CLK pin, when work under 3D PS2 mouse function. Default value is 1. USB_STAT Register
Bit No. 0 1 2 3 4~7
Label EP0EN EP1EN EP2EN EP3EN 3/4
Function Control the USB endpoint0 interrupt (1=enabled; 0=disabled) Control the USB endpoint1 interrupt (1=enabled; 0=disabled) Control the USB endpoint2 interrupt (1=enabled; 0=disabled) Control the USB endpoint3 interrupt (1=enabled; 0=disabled) Unused bit, read as 0 UINT1 Register
Rev. 1.10
71
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
Bit No. 0 Label SUSP Function Read only, USB suspend indication. When this bit is set to 1 (set by SIE), it indicates that the USB bus has entered the suspend mode. The USB interrupt is also triggered when this bit changes from low to high. USB remote wake-up command. It is set by MCU to leave the USB host leaving the suspend mode. USB reset indication. This bit is set/cleared by the USB SIE. This bit is used to detect a USB reset event on the USB bus. When this bit is set to 1, this indicates that a USB reset has occurred and that a USB interrupt will be initialized.
1
RMWK
2
URST
3
USB resume indication. When the USB leaves the suspend mode, this bit is set to 1 (set by SIE). When the RESUME is set by SIE, an interrupt will be generated to wake-up the MCU. In order to detect the suspend state, the MCU should set USBCKEN and clear RESUME SUSP2 (in the UCC register) to enable the SIE detect function. RESUME will be cleared when the SUSP goes to 0. When the MCU is detecting the SUSP, the condition of RESUME (causes the MCU to wake-up) should be noted and taken into consideration. V33O PLL SELPS2 URD 0/1: Turn-off/on V33O output. 0: Turn-on PLL (default), 1: turn off PLL. When set to 1, indicated the chip work under PS2 mode. Default value is 0. USB reset signal control function definition. 1: USB reset signal will reset MCU. 0: USB reset signal cannot reset MCU. USC Register
4 5 6 7
The USR register which is the endpoint interrupt status register, is used to indicate which endpoint is accessed and to select the USB bus. The endpoint request flags, EP0F, EP1F, EP2F and EP3F, are used to indicate which endpoints are accessed. If an endpoint is accessed, the related endpoint request flag will be set high and a USB interrupt will be generated, if the USB interrupt is enabled and the stack is not full. When the active endpoint request flag is serviced, the endpoint request flag has to be cleared to zero using the program. Bit No. 0 Label EP0F Function When this bit is set to 1 (set by SIE), it indicates that endpoint 0 has been accessed and a USB interrupt will occur. When the interrupt has been serviced, this bit should be cleared by software. When this bit is set to 1 (set by SIE), it indicates that endpoint 1 has been accessed and a USB interrupt will occur. When the interrupt has been serviced, this bit should be cleared by software. When this bit is set to 1 (set by SIE), it indicates that endpoint 2 has been accessed and a USB interrupt will occur. When the interrupt has been serviced, this bit should be cleared by software. When this bit is set to 1 (set by SIE), it indicates that endpoint 3 has been accessed and a USB interrupt will occur. When the interrupt has been serviced, this bit should be cleared by software. Unused bit, read as 0 USR Register
1
EP1F
2
EP2F
3 4~7
EP3F 3/4
Rev. 1.10
72
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
There is a system clock control register to select the clock used in the MCU. This register consists of a USB clock control bit, USBCKEN, a second suspend mode control bit, SUSP2, and a system clock selection bit, SYSCLK. The endpoint selection is determined by EPS2, EPS1 and EPS0. Bit No. Label Function Accessing endpoint FIFO selection. EPS2, EPS1, EPS0: 000: Select endpoint 0 FIFO (control) 001: Select endpoint 1 FIFO 010: Select endpoint 2 FIFO 011: Select endpoint 3 FIFO If the selected endpoints do not exist, the related functions will be absent. USB clock control bit. When this bit is set to 1, it indicates that the USB clock is enabled. Otherwise, the USB clock is turned-off. This bit is used for reducing power consumption in suspend mode. In normal mode, clean this bit to 0. In halt mode, set this bit to 1 for reducing power consumption. This bit is used to define if the MCU system clock comes form an external OSC or comes from the PLL output 16MHz clock. 0: system clock sourced from OSC. 1: system clock sourced from the PLL output 16MHz. This bit is used to specify the MCU system clock oscillator frequency. For a 6MHz crystal oscillator or resonator, set this bit to 1. For a 12MHz crystal oscillator or resonator, clear this bit to 0. This bit is used to control whether there is 7.5kW resistor between D+ and Vbus. 0: no 7.5kW between D+ and Vbus (default) 1: has 7.5kW between D+ and Vbus UCC Register The AWR register contains the current address and a remote wake up function control bit. The initial value of AWR is 00H. The address value extracted from the USB command has not to be loaded into this register until the SETUP stage has finished. Bit No. 0 1~7 Label WKEN Function USB remote-wake-up enable/disable (1/0)
0 1 2
EPS0 EPS1 EPS2
3
USBCKEN
4
SUSP2
5
FSYS16MHz
6
SYSCLK
7
RCTRL
AD0~AD6 USB device address AWR Register
The STALL register shows if the corresponding endpoint has worked properly or not. As soon as endpoint improper operation occurs, the related bit in the STALL register has to be set high. The STALL register bits will be cleared by a USB reset signal and a setup token event. Bit No. 0~3 4~7 Label STL0~ STL3 3/4 Function Set by the users when related USB endpoints were stalled. Cleared by a USB reset. The STL0 is also cleared by a Setup Token event. Unused bit, read as 0 STALL Register
Rev. 1.10
73
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
The SIES register is only used for EP0 except for the NMI bit, which can control all endpoints Bit No. Label Function This bit is used to configure the SIE to automatically change the device address by the value stored in the AWR register. When this bit is set to 1 by firmware, the SIE will update the device address by the value stored in the AWR register after the PC host has successfully read the data from he device by an IN operation. Otherwise, when this bit is cleared to 0, the SIE will update the device address immediately after an address is written to the AWR register. So, in order to work properly, the firmware has to clear this bit after a next valid SETUP token is received. This bit is used to indicate that some errors have occurred when the FIFO is accessed. This bit is set by SIE and should be cleared by firmware. This bit is used for all endpoint This bit is used to indicate the OUT token (except the OUT zero length token) has been received. The firmware clears this bit after the OUT data has been read. Also, this bit will be cleared by SIE after the next valid SETUP token is received. This bit is used to indicate the current USB receiving signal from PC host is IN token. This bit will set to 1 once SIE discover ther are some error condition so the SIE is not response (NAK or ACK or DATA) for the USB token. This bit is set by SIE and clear by F/W. Unused bit, read as 0 This bit will set to 1 when there are the following three condition is happened: CRC error, PID error, Bit stuffing error. This bit is set by SIE and clear by F/W. NAK token interrupt mask flag. If this bit set, when the device sent a NAK token to the host, an interrupt will be disabled. Otherwise if this bit is cleared, when the device sends a NAK token to the host, it will enter the interrupt sub-routine. This bit is used for all endpoint. SIES Register The MISC register combines command and status to control the desired endpoint FIFO action and to show the status of the desired endpoint FIFO. MISC will be cleared by a USB reset signal. Bit No. 0 Label REQUEST Function After setting the status of the desired one, FIFO can be requested by setting this bit high. After finishing, this bit must be set low. To represent the direction and transition end MCU access. When set to logic 1, the MCU desires to write data to the FIFO. After finishing, this bit must be set to logic 0 before terminating request to represent transition end. For an MCU read operation, this bit must be set to logic 0 and set to logic 1 after finishing. MCU requests to clear the FIFO, even if the FIFO is not ready. After clearing the FIFO, the USB interface will send force_tx_err to tell the Host that data under-run if the Host wants to read data. Unused bit, read as 0 To show that the data in the FIFO is a setup command. This bit is set by Hardware and clear by Firmware. To show that the desired FIFO is ready. To show that the host sent a 0-sized packet to the MCU. This bit must be cleared by a read action to the corresponding FIFO. MISC Register
0
ASET
1
ERR
2 3 4 5 6
OUT IN NO ACK 3/4 CRCF
7
NMI
1
TX
2 3~4 5 6 7
CLEAR 3/4 SETCMD READY LEN0
Rev. 1.10
74
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
Bit No. 0 1 2 3 4~7 Note: Label FIFO_def SETI1* SETI2* SETI3* 3/4 Function Once this bit set to 1 by Firmware, The SIE should redefine the FIFO configuration. This bit is automatically cleared by SIE Input FIFO for EP1 eanble 1/disable 0; default disable Input FIFO for EP2 eanble 1/disable 0; default disable Input FIFO for EP3 eanble 1/disable 0; default disable Unused bit, read as 0
* It is only required to set the data pipe as an input pile or output pile. The purpose of this function is to avoid the host sending an abnormal IN or OUT token and disabling the endpoint. UFIEN Register, USB Endpoint 1~Endpoint 3 set IN Pipe Enable Register.
Bit No. 0 1 2 3 4~7 Note:
Label DATATG* DATA token toggle bit SETO1** SETO2** SETO3** 3/4
Function
Output FIFO for EP1 eanble 1/disable 0; default disable Output FIFO for EP2 eanble 1/disable 0; default disable Output FIFO for EP3 eanble 1/disable 0; default disable Unused bit, read as 0
* USB definition: when the host sends a set Configuration, the Data pipe should send the DATA0 (about the Data toggle) first. So, when the Device receives a set configuration setup command, the user needs to toggle this bit as the following data will send a Data0 first. ** It is only required to set the data pipe as an input pile or output pile. The purpose of this function is to avoid the host sending a abnormal IN or OUT token and disabling the endpoint. UFOEN Register, USB Endpoint 1~Endpoint 3 set OUT pipe enable register
Bit No. 0 1
Label
Function
00: RAM0 input FIFO, RAM1 output FIFO RAM_def0 01: Both RAM0 and RAM1 are output FIFO RAM_def1 10: Both RAM0 and RAM1 are input FIFO 11: RAM0 output FIFO, RAM1 input FIFO Define endpoint 1 FIFO size E1FS1, E1FS0: 00: 8-byte 01: 16-byte 10: 32-byte 11: 64-byte Define endpoint 2 FIFO size E2FS1, E2FS0: 00: 8-byte 01: 16-byte 10: 32-byte 11: 64-byte Define endpoint 3 FIFO size E3FS1, E3FS0: 00: 8-byte 01: 16-byte 10: 32-byte 11: 64-byte UFC0 USB FIFO Size Control Register 0
2 3
E1FS0 E1FS1
4 5
E2FS0 E2FS1
6 7
E3FS0 E3FS1
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75
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HT82A623R/HT82A6208/HT82A6216
The total FIFO size is 64+8 bytes. All endpoints except EP0 can be defined by registers UFOEN, UFIEN, UFC0 and UFC. There are three FIFO mapped as follow: 8 bytes FIFO for Endpoint0 RAM0 FIFO for other input Endpoint (1~3) RAM1 FIFO for other output Endpoint (1~3) Bit No. 0~3 4~7 Label FIFO0~ FIFO3 3/4 Function EPi accessing register (i=0~3). When an endpoint is disabled, the corresponding accessing register should be disabled. Unused bit, read as 0 FIFO0~FIFO3 USB endpoint accessing registers definitions
Configuration Options
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Options PA pull-high enable/disable (1/0) (default: enable) PB pull-high enable/disable (1/0) by nibble (default: enable) PC pull-high enable/disable (1/0) by nibble (default: enable) PC, wake-up enable/disable (1/0) by nibble (default: disable) SPIA WCOL: Enable/Disable (default disable) Built-in 1.5K (default no built-in) Has 7.5kW resistor enable bit (default no) TBHP enable or disable (default disable) Low voltage reset: enable/disable (default: enable) WDT enable/disable (0/1) (default: enable) WDT clock source: fSYS/4 or RC (default T1) CLR WDT instructions: one or two clear WDT instruction(s) (0/1) (default: 1 inst.) PA NMOS or CMOS output type (default CMOS) Port A wake-up enable/disable (1/0) by bit (default: enable) PB0~PB3 NMOS or CMOS output type (default CMOS) Port B wake-up enable/disable (1/0) by bit (default: disable) 0: PB7 used as GPIO 1: PB7 used as VDDIO pin 0: PB0~PB6 use power=VDD 1: PB0~PB6 use power=VDDIO PD NMOS or CMOS output type (default CMOS) PD pull-high enable/disable (1/0) by nibble (default: enable) PD, wake-up enable/disable (1/0) by nibble (default: disable) SPIB WCOL: enable/disable (default disable)
Rev. 1.10
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HT82A623R/HT82A6208/HT82A6216
Application Circuits
Crystal or Ceramic Resonator for Multiple I/O Applications
VDD USBUSB+ VSS
0 .1 m F * VDD
PA0~PA7 PB0~PB7 PC0~PC7 PD0~PD7 OSC1
10mF*
100kW
0 .1 m F * *
V33O
0 .1 m F
1 .5 k W
X1
OSC2 U S B D -/D A T A
33W
RES
0 .1 m F
VSS
U S B D + /C L K
33W
Note:
The resistance and capacitance for the reset circuit should be designed in such a way as to ensure that VDD is stable and remains within a valid operating voltage range before bringing RES high. X1 can be 6MHz or 12MHz, and should be located as close to the OSC1/OSC2 pins as possible. * These capacitors should be placed close to the USB connector. ** This capacitor should be placed close to the MCU.
Rev. 1.10
77
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
Instruction Set
Introduction C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be CLR PCL or MOV PCL, A. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
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Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the SET [m].i or CLR [m].i instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] INCA [m] INC [m] DECA [m] DEC [m]
Description Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory
Cycles 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 1 1Note 1 1Note
Flag Affected Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Logic Operation
Increment & Decrement
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Mnemonic Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Description Cycles Flag Affected
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
Rev. 1.10
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October 30, 2009
HT82A623R/HT82A6208/HT82A6216
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Operation Affected flag(s) ADD A,x Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND A,x Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Rev. 1.10 Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ACC + [m] + C OV, Z, AC, C Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. ACC ACC + [m] OV, Z, AC, C Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ACC + x OV, Z, AC, C Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ACC + [m] OV, Z, AC, C Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ACC AND [m] Z 81 October 30, 2009
HT82A623R/HT82A6208/HT82A6216
CALL addr Description Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack Program Counter + 1 Program Counter addr None Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] 00H None Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i 0 None Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF
Operation
Affected flag(s) CLR [m] Description Operation Affected flag(s) CLR [m].i Description Operation Affected flag(s) CLR WDT Description Operation
Affected flag(s) CLR WDT1 Description
Operation
Affected flag(s) CLR WDT2 Description
Operation
Affected flag(s)
Rev. 1.10
82
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
CPL [m] Description Operation Affected flag(s) CPLA [m] Description Complement Data Memory Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC [m] Z Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ACC + 00H or [m] ACC + 06H or [m] ACC + 60H or [m] ACC + 66H C Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] [m] - 1 Z Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] - 1 Z Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO 0 PDF 1 TO, PDF
Operation Affected flag(s) DAA [m] Description
Operation
Affected flag(s) DEC [m] Description Operation Affected flag(s) DECA [m] Description Operation Affected flag(s) HALT Description
Operation
Affected flag(s)
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October 30, 2009
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INC [m] Description Operation Affected flag(s) INCA [m] Description Operation Affected flag(s) JMP addr Description Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] [m] + 1 Z Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] + 1 Z Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter addr None Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC [m] None Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC x None Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ACC None No operation No operation is performed. Execution continues with the next instruction. No operation None Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR [m] Z
Operation Affected flag(s) MOV A,[m] Description Operation Affected flag(s) MOV A,x Description Operation Affected flag(s) MOV [m],A Description Operation Affected flag(s) NOP Description Operation Affected flag(s) OR A,[m] Description Operation Affected flag(s)
Rev. 1.10
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October 30, 2009
HT82A623R/HT82A6208/HT82A6216
OR A,x Description Operation Affected flag(s) ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) RET A,x Description Operation Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ACC OR [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter Stack None Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter Stack ACC x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter Stack EMI 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 [m].7 None
Affected flag(s) RETI Description
Operation
Affected flag(s) RL [m] Description Operation
Affected flag(s) RLA [m] Description
Operation
Affected flag(s)
Rev. 1.10
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October 30, 2009
HT82A623R/HT82A6208/HT82A6216
RLC [m] Description Operation Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 C C [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 C C [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 None Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 C C [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 C C [m].0 C
Affected flag(s) RLCA [m] Description
Operation
Affected flag(s) RR [m] Description Operation
Affected flag(s) RRA [m] Description
Operation
Affected flag(s) RRC [m] Description Operation
Affected flag(s) RRCA [m] Description
Operation
Affected flag(s)
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86
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
SBC A,[m] Description Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] - C OV, Z, AC, C Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] - C OV, Z, AC, C Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] - 1 Skip if [m] = 0 None Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC [m] - 1 Skip if ACC = 0 None Set Data Memory Each bit of the specified Data Memory is set to 1. [m] FFH None Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i 1 None
Operation Affected flag(s) SBCM A,[m] Description
Operation Affected flag(s) SDZ [m] Description
Operation Affected flag(s) SDZA [m] Description
Operation
Affected flag(s) SET [m] Description Operation Affected flag(s) SET [m].i Description Operation Affected flag(s)
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SIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] + 1 Skip if [m] = 0 None Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] + 1 Skip if ACC = 0 None Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] OV, Z, AC, C Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] OV, Z, AC, C Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - x OV, Z, AC, C
Operation Affected flag(s) SIZA [m] Description
Operation Affected flag(s) SNZ [m].i Description
Operation Affected flag(s) SUB A,[m] Description
Operation Affected flag(s) SUBM A,[m] Description
Operation Affected flag(s) SUB A,x Description
Operation Affected flag(s)
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October 30, 2009
HT82A623R/HT82A6208/HT82A6216
SWAP [m] Description Operation Affected flag(s) SWAPA [m] Description Operation Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 [m].7 ~ [m].4 None Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3 ~ ACC.0 [m].7 ~ [m].4 ACC.7 ~ ACC.4 [m].3 ~ [m].0 None Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m] = 0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] Skip if [m] = 0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i = 0 None Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None
Affected flag(s) SZ [m] Description
Operation Affected flag(s) SZA [m] Description
Operation Affected flag(s) SZ [m].i Description
Operation Affected flag(s) TABRDC [m] Description Operation
Affected flag(s) TABRDL [m] Description Operation
Affected flag(s)
Rev. 1.10
89
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
XOR A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ACC XOR [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR x Z
Rev. 1.10
90
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
Package Information
28-pin SOP (300mil) Outline Dimensions
28 A
15 B
1
14
C C' G H D E F
a
* MS-013
Symbol A B C C D E F G H a
Dimensions in mil Min. 393 256 12 697 3/4 3/4 4 16 8 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 713 104 3/4 12 50 13 8
Rev. 1.10
91
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
28-pin SSOP (150mil) Outline Dimensions
28 A
15 B
1 C C'
14
G H a F
D E
Symbol A B C C D E F G H a
Dimensions in mil Min. 228 150 8 386 54 3/4 4 22 7 0 Nom. 3/4 3/4 3/4 3/4 3/4 25 3/4 3/4 3/4 3/4 Max. 244 157 12 394 60 3/4 10 28 10 8
Rev. 1.10
92
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
SAW Type 48-pin (7mm7mm) QFN Outline Dimensions
D 37 b 36
D2 48 1
E e 25 A1 A3 A L K 24 13 12
E2
Symbol A A1 A3 b D E e D2 E2 L K
Dimensions in mm. Min. 0.70 0.00 3/4 0.18 3/4 3/4 3/4 4.50 4.50 0.30 0.20 Nom. 3/4 3/4 0.203 3/4 7.0 7.0 0.50 3/4 3/4 3/4 3/4 Max. 0.80 0.05 3/4 0.30 3/4 3/4 3/4 5.75 5.75 0.50 3/4
Rev. 1.10
93
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
44-pin QFP (10mm10mm) Outline Dimensions
C D G 23 33
H
I 34 22 L F A B E 44 12 K 1 11 a J
Symbol A B C D E F G H I J K L a
Dimensions in mm Min. 13.0 9.9 13.0 9.9 3/4 3/4 1.9 3/4 0.25 0.73 0.1 3/4 0 Nom. 3/4 3/4 3/4 3/4 0.8 0.3 3/4 3/4 3/4 3/4 3/4 0.1 3/4 Max. 13.4 10.1 13.4 10.1 3/4 3/4 2.2 2.7 0.50 0.93 0.2 3/4 7
Rev. 1.10
94
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
52-pin QFP (14mm14mm) Outline Dimensions
C D 39 27 G H
I 40 26 F A B E
52
14 K J 1 13
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 17.30 13.90 17.30 13.90 3/4 3/4 2.50 3/4 3/4 0.73 0.10 0 Nom. 3/4 3/4 3/4 3/4 1.00 0.40 3/4 3/4 0.10 3/4 3/4 3/4 Max. 17.50 14.10 17.50 14.10 3/4 3/4 3.10 3.40 3/4 1.03 0.20 7
Rev. 1.10
95
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SOP 28W (300mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.01.0 100.01.5 13.0
+0.5/-0.2
2.00.5 24.8
+0.3/-0.2
30.20.2
SSOP 28S (150mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.01.0 100.01.5 13.0
+0.5/-0.2
2.00.5 16.8
+0.3/-0.2
22.20.2
Rev. 1.10
96
October 30, 2009
HT82A623R/HT82A6208/HT82A6216
Carrier Tape Dimensions
D
E F W C
P0
P1
t
B0
D1
P A0
K0
R e e l H o le p a c k a g e p in 1 a n d th e r e e l h o le s a r e lo c a te d o n th e s a m e s id e . IC
SOP 28W (300mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.00.3 12.00.1 1.750.10 11.50.1 1.5 1.50
+0.1/-0.0 +0.25/-0.00
4.00.1 2.00.1 10.850.10 18.340.10 2.970.10 0.350.01 21.30.1
SSOP 28S (150mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Description Carrier Tape Width Dimensions in mm 16.00.3 8.00.1 1.750.1 7.50.1 1.55 1.50
+0.10/-0.00 +0.25/-0.00
4.00.1 2.00.1 6.50.1 10.30.1 2.10.1 0.300.05 13.30.1 97 October 30, 2009
Rev. 1.10
HT82A623R/HT82A6208/HT82A6216
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2009 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.10
98
October 30, 2009

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